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DS90UB913A-Q1: how to exercise flow control with different clock for camera sensor than the serializer

Part Number: DS90UB913A-Q1

Below is the data link for our set up

megapixel sensor -> fpga -> DS90UB913 serializer -> DS90UB934 deserializer -> TDA2x

The sensor runs at a different clock than the serializer.  What is the mechanism in the serializer for the fpga to possibly exercise flow control of the sensor data?

Can we use the HSYNC and VSYNC signals in the serializer for flow control?  If yes, are there timing diagrams to demonstrate the use of HSYNC and VSYNC for this purpose?

Thanks.

  • Hello,
    There are different clocking modes in the serializer such as using an external oscillator as the reference clock source for the PLL or PCLK from the imager as primary reference clock to the PLL (make sure the clock from the imager is clean from a jitter point of view).
    Please refer to the 913A datasheet section 8.4 for additional information.
  • In the data link above, the fpga will buffer a line or two of the image sensor. The current thinking is to have the fpga output the pclk to the deserializer.

    Are there timing diagrams available for using the HSYNC or VSYNC to throttle data from the fpga to the deserializer? There are no such diagrams in the 913A datasheets.
  • Hello,

    The H and V sync do not control the video data coming out of the serializer.  ​If the H and V sync are missing the video data will still be transmitted on the serial FPD link.  See the HSYNC and VSYNC pin descriptions and section 8.1 of the datasheet for restrictions on H and V sync. 

    Mike

  • If H and V sync do not control the video data coming out of the serializer, are there other signals on the serializer that can be used for this purpose?
  • My question above refers to inputs for the serializer such that the serializer could listen to and decide to wait if data is not yet ready from the fpga.
  • Hello,

    There is not a way possible to automatically turn off the FPD link, depending on the input into the serializer. These parts are designed to keep the FPD link going when they are on.

    One possibility is for the FPGA to control the PDB pin. When it is not transmitting, the FPGA would hold the PDB pin low. When it is ready to transmit it would need to pull PDB high and setup the registers in the 913 and then transmit. There is a delay from the time that PDB goes high to when the output of the serializer is active, see figure 9 in the datasheet.

    Another way that might also work is doing the same as above but instead of using PDB, writing to bit 3 of register 0x01. This is something that you would need to try to see if it works the way you are looking for.

    Mike
  • It's not in the plan to turn off the serializer using the PDB pin, as this is disruptive.

    We researched a bit more into the TDA2x, also a TI part. In the very long TDA2x datasheet, Section 9 on Video Input Port (VIP), it does provide examples of using HSYNC and VSYNC for indicating the start of valid data. Examples would be Figure 9-33 to Figure 9-37.
  • Hello,
    We understand your suggestion, but this type function is not supported by the DS90UB913A device. Typically the serializer - deserializer link can be brought up and stable in less than 100ms, so the majority of use case would turn off the link for any extended time it woudl not be needed.

    Regards,