Other Parts Discussed in Thread: DS100MB203
Hi,
Flow of data is as shown in the attached document.
DS100 and tlk10034 are in 10GBaseKR mode.
The DS100 settings for channel are as follows:
Register ->Value:
0x0f->0x0
0x17->0xa8
0x18->0x0.
With these values the 10GBaseKR link is up.But the register CHANNEL_STATUS_1 (0x1E.0x000F) of TLK10034 read as 0X5D03 and 0x5C03 . The value is not stable and oscillating between the two.The bit HS_DECODE_INVALID is getting set frequently. What causes this bit (HS_DECODE_INVALID) to get set?
Can changing any register of TLK prevent this ? Is there any threshold setting which can be altered to increase the margin so that decode invalid will not be set frequently?
Thanks,
Ashitha