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[FAQ] DS250DF410: How to setup PRBS pattern generation/checker using divide by 2, 4, or 8 clock

Part Number: DS250DF410

Using a simple clock, DS250DFxxx and DS280DFxxx can generate different prbs patterns at different data rate up to 28Gbps. To make it very simple, SigconArchitect can be used to achieve this goal. What are the steps to do this?

 

  • In this example, 12.5GHz, 6.25GHz, or 3.125GHz clock can be used as input to RXP0/RXN0 pins to enable TXP0/TXN0 to generate PRBS31 pattern at 25Gbps. Externally, TXP0/TXN0 is connected to RXP1/ RXN1 pins and we will confirm 25Gbps PRBS31 error free operation. In this example, we use SigconArchitect GUI. In another post, we do the same but through registers.

    Use SigconArchitect Software:After confirming software communicates with evaluation board or device under test, below are steps to setup GUI:
    a. Using differential SMA cables, connect from clock source to evaluation board
    b. Using differential SMA cables, connect from TXP0/TXN0 to RXP0/RXN0.
    c. Enable clock to RXP0/RXN0 pins. Confirm current consumption increase in order of 50mA to 150mA when clock is turned on.
    d. Using GUI, go to CDR tab, enable device to lock to 25Gbps, and click on Apply to All Channels:
    e. Go to PRBS Gen/Check tab. Make sure Channel Select is Channel 0, Pattern Type PRBS31, and then click Enable*. Next verify Signal Detected and CDR Locked LEDs for channel 0 are green.
    f. PRBS Checker: Change Channel Select to Channel 1 and confirm Channel Indicators show green LEDs for channel 1 Signal Detected and CDR Locked. Next click on "Turn On*" button. Confirm pattern type is PRBS31, data rate is 25Gbps, with zero error count.

     

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