This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83867IR: MDIO level is divided after DP83867IR chip Reset pin is released!!

Part Number: DP83867IR

Using DP83867IRPAP on a custom board with Texas TMS320DM6467TCUTD1.

The MDIO line seems to be getting pulled low by the PHY. I have a 2.2k pull-up to VDDIO, which is 3.3V. When PHY RESETN is low, MDIO is pulled high to 3.3V, as expected. Once PHY is taken out of reset, MDIO is being pulled low by something. When MAC talks, Vhigh is only about 3.27V. When the PHY responds, Vhigh is only about 1.6V. When neither the MAC nor the PHY are communicating, MDIO is pulled back low.

If I put PHY in reset and send out read requests from the MAC, then the levels are correct.

What could be pulling MDIO low?

The schematic file has been attached.

Thanks

TIQ.pdf