• State TI Thinks Resolved
  • Locked Locked
  • Replies 12 replies
  • Answers 1 answer
  • Subscribers 31 subscribers
  • Views 1560 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

XIO3130: communication issue between XIO3130 and Wi-Fi Module

Dhaivat Master
Intellectual 385 points
Part Number: XIO3130

We are using XIO3130 in our design. On upstream port, we have NXP P1020 and on downstream port we have three Wi-Fi module.
We are having issue with the XIO3130 and Wi-Fi module communication. We uploaded the EEPROM with configuration file
but still we are not able to communicate with Wi-Fi modules. 

If you can provide me an email I want you to have a look at the schematic.

Thanks,
Dhaivat 

  • 0
    TI__Guru 64326 points
    Dhaivat,

    You can private message me the schematic through E2E. How are you testing the communication from NXP P1020 to Wi-Fi module?
  • 0 in reply to Malik Barton57
    Intellectual 385 points
    Malik Barton,

    We are trying to read the register on Wi-Fi Module. We are not getting any data while booting and in process.
  • 0 in reply to Dhaivat Master
    TI__Guru 64326 points
    Dhaivat,

    Are you able to read the Status Register of any of the downstream ports on the PCIE bus?
  • 0 in reply to Malik Barton57
    Intellectual 385 points

    Malik Barton,

    Yes, we are able to read the downstream and upstream port register by 'setpci' command.

  • 0 in reply to Dhaivat Master
    TI__Guru 64326 points
    Dhaivat,

    After reviewing your schematic I could not find anything that would cause an issue. Could you describe you issue in more detail so that I have a full understanding? Is there no communication through the main PCIe link between Upstream and downstream ports or is the failed communication through other means? Since the schematic is dense I will give a second look to make sure I did not miss anything.
  • 0 in reply to Malik Barton57
    Intellectual 385 points
    Malik Barton,

    There is no problem with XIO3130 upstream port. Communication is present between P1020 and XIO3130 but there is no communication on downstream port (between XIO3130 and Wi-Fi Module). We are not able to configure the Wi-Fi module which are connected on downstream port and also not getting any kind of data from it.
  • 0 in reply to Dhaivat Master
    Intellectual 275 points

    Hi Malik Barton,

    I think we have one GPIO pin need control on WiFI module, and the circuit connect to XIO3130's GPIO5. We  try to access the upstream register 0xBE and set the value to 0x1249, and read register again, and the value is the same 0x1249. When we write the data to register 0xC4 and value is 0x7FFFF, but read again the value always 0x37fd8. It can't change it. Can we direct control the GPIO from upstream register? Thanks!!

    Regards,

    Kevin

  • 0 in reply to Kevincy
    TI__Guru 64326 points

    Kevin,

    I believe you should be able to control the GPIO from the upstream register. It seems that you are writing to 0xBE making GPIO5 to be a general purpose output. then you write to 0xC4 a 0x7FFFF. This should set GPIO5 high, see PCIE_GPIO5_DATA bit 5 of the 0xC4 register. When reading this register you are getting the current state of the GPIOs, if the GPIOs are not configured as general purpose outputs the writes may not have the same effect. Therefore you may not get back 0x7FFFF every time. Looking at just bit 5 of register 0xC4 the write of 1 is read back. Can you try to toggle just GPIO5 high and low to see if you read the correct values? 

    • Write 0x7FFEF
    • Then read the register back, expected value: 0x37FC8
    • Write 0x7FFFF
    • Then read the register back, expected value: 0x37FD8
  • 0 in reply to Malik Barton57
    Intellectual 275 points

    Hi Malik Barton,

    We check your suggestion, but in datasheet the GPIO5 is bit5 and it should be on position 6. Anyway we check 0xE and 0xD for GPIO5, and read/write it.

    But the result is same, nothing change, in below. Any ideal?

    Write 0x7FFEF --> Read --> 0x37fd8

    Write 0x7FFDF --> Read --> 0x37fd8

    Write 0x7FFFF --> Read --> 0x37fd8

    Regards,

    Kevin

  • 0 in reply to Kevincy
    TI__Guru 64326 points

    Kevin,

    My apologies for the mistake. Are you writing these values to a EEPROM? It may be that a PCIe bus reset is necessary for the changes to take place could you try resetting the bus in between writes and reads to see if this effects GPIO5 status. 

  • 0 in reply to Malik Barton57
    Intellectual 275 points
    Hi Malik Barton,

    We have no way write value to eeprom. Could we access eeprom from updtream register, and how to do it? Thanks!!

    Regards,
    Kevin
  • 0 in reply to Kevincy
    TI__Guru 64326 points

    Kevin,

    This is possible, please follow the steps listed in section 3.4.4 Accessing Serial Bus Devices Through Software of the XIO3130 data manual (link below). Also please refer to Table 3-3. EEPROM Register Loading Map for information on how the EEPROM addresses maps to the upstream/downstream registers.