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TLK10232: TLK10232 is not able to link up on 1G-KX

Prodigy 165 points

Replies: 30

Views: 2344

Part Number: TLK10232

Dear TI developers, 

We have product using TLK10232, we want to bring up on new platform. 

Somehow we cannot get 1G-KX link up properly, we want to inquiry with you in detail. 

The previous platform has a GE switch with 2 ports connect to TLK10232 HS; 

Channel A is 10G-KX and Channel B is 1G-KX.

Based on the attachment, we can use the 'init sequence' + 'setup loopback on same port' to get TLK10232 link up on 10G-KR;  

and using 'init sequence' + '1G-KX setting' + 'setup loopback on same port' to get TLK10232 link up on 1G-KX.

The new platform is using Intel CPU w/ X552 10 GbE Backplane connect to TLK10232 HS. 

We want to using the same sequence as old platform to get link up, 

We are able to get 10G-KR link up, but failed on 1G-KX portion. 

Since the new platform, the HS media is changed,

Do you suggest to modify the setting for  0x1e.[2-5], which are related to  HS_SERDES_CONTROL ? 

If yes, I think the Intel x552 10GbE is common component,

Do you have the experience for configure these HS_SERDES_CONTROL? 

Thank you.

Alan

  • Alan,

    I am looking into your issues and will get back to you as soon as possible.

  • In reply to Malik Barton57:

    Hi, Malik,

    Thanks for tracking and response.

    We tried to tune the best value of HS_SERDES_CONTROL_3 this weekend;
    The algorithm is base on my previous attachment, and loop the CTRL_3 value from 0x0 to 0xFFFF,
    keep HS_SERDES_CONTROL_2 as 0xe888, If it is able to link up, then we try it again.
    If the value is good and stable, it must jump into infinite loop w/ good value.

    The result shows we only have 0x4291 and 0x43f2 link up 4 times. The others are less than 4 times or no link up.
    It seems we are going to a wrong debug direction...

    We will try the same algorithm but removing the steps related to configure 'magic register' on init seq and using default value (0xa848) on HS_SERDES_CONTROL_2 today.
    Will let you know the result soon.

    If you have any advise, please let us know.

    Thank you.
    Alan
  • In reply to Alan Peng:

    one more question,

    Do you think it would help
    if we write a state machine to toggle LT_TRAIN_CONTROL register 1.0x96 bit[0] and poll LT_TRAIN_STATUS register 1.0x97
    right after the 3 seq : 'init seq' + '1g-kx setting' + 'setup loopback on same port' ?

    Thank you.
    Alan
  • In reply to Alan Peng:

    Alan,

    I do not advise using LT with the internal loopback mode of the device. Instead try HS_AGCCTRL[1:0] = 0x4 instead of HS_AGCCTRL[1:0] = 0x8. This may have affected your tuning of HS_SERDES_CONTROL_3. 

  • In reply to Malik Barton57:

    Hi, Malik, 

    We found some values of CTL_2 and CTL_3 are able to get link up, but failed on 2nd time easily.

    Later on we found adding delay after each configure stage is able to get link up without change CTL_2 and CTL_3 value, but it needs retry many times. 

    for example:

    RETRY with { [ 'Init seq' + DELAY + '1G-KX setting' + DELAY +  'set same channel HS input (0x1E.0x18  |= 0x4000)' + DELAY + 'setup deep remote loopback ' + DELAY  ] break if link up } 

    The DELAY cannot be less than 96 ms and also cannot large than 120 ms, otherwise it cannot link up even with retry. 

    The RETRY range is 1-60 times for overnight testing.  (60 times.. This is not acceptable..)

    If it is 10G-KR, we don't need these 'DELAY and 1G-KX setting then poll Intel backplane eth port status for link up.  

    Do you have any suggestion? is it possible 1G SI between Intel and TLK is not good? 

    Thank you.

    Alan

  • In reply to Alan Peng:

    Alan,

    I am still looking into your issue but have not found a complete solution as of yet. I will update you when I have something more concrete. 

  • In reply to Malik Barton57:

    Hi, Malik,

    Thanks for update.
    Please let us know if there is anything worth to try.


    Thank you.
    Alan
  • In reply to Alan Peng:

    Alan,

    Sorry for the late response. I have note been able to replicate or find similar issues to yours. The SI of the 1G-KX may be the issue here. Are there any differences in implementation between the 1G-KX and 10G-KR links in terms of trace length, cables or connector?
  • In reply to Malik Barton57:

    Malik,

    It's a typo for 'note' -> 'not' right?
    Is this mean you are able to get link up using TLK10232 with Intel X550 series backplane for both 1G-KX and 10G-KR?

    Since TLK10232 is connected to backplane, the connection environment must be the same between 10G-KR and 1G-KX.
    Unless x552 divide 1G and 10G to the different route.

    Thank you.
    Alan
  • In reply to Alan Peng:

    Alan,

    Sorry for the late reply. Yes that was a typo. I did not use your specific backplane when running my simple test. My leading suspicion is that the SI between the TLK10232 and Intel X550 is not good. Just to be clear you are still not able to get a reliable link up when testing in deep remote loopback correct? Have you tried adding a data path reset in your testing algorithm? For example:

    RETRY with { [ 'Init seq' + DELAY + '1G-KX setting' + DELAY + 'set same channel HS input (0x1E.0x18 |= 0x4000)' + Data path reset + 'setup deep remote loopback ' + DELAY ] break if link up }

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