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TLK10232: TLK10232 is not able to link up on 1G-KX

Part Number: TLK10232

Dear TI developers, 

We have product using TLK10232, we want to bring up on new platform. 

Somehow we cannot get 1G-KX link up properly, we want to inquiry with you in detail. 

The previous platform has a GE switch with 2 ports connect to TLK10232 HS; 

Channel A is 10G-KX and Channel B is 1G-KX.

Based on the attachment, we can use the 'init sequence' + 'setup loopback on same port' to get TLK10232 link up on 10G-KR;  

and using 'init sequence' + '1G-KX setting' + 'setup loopback on same port' to get TLK10232 link up on 1G-KX.

The new platform is using Intel CPU w/ X552 10 GbE Backplane connect to TLK10232 HS. 

We want to using the same sequence as old platform to get link up, 

We are able to get 10G-KR link up, but failed on 1G-KX portion. 

Since the new platform, the HS media is changed,

Do you suggest to modify the setting for  0x1e.[2-5], which are related to  HS_SERDES_CONTROL ? 

If yes, I think the Intel x552 10GbE is common component,

Do you have the experience for configure these HS_SERDES_CONTROL? 

Thank you.

Alan

  • Alan,

    I am looking into your issues and will get back to you as soon as possible.

  • Hi, Malik,

    Thanks for tracking and response.

    We tried to tune the best value of HS_SERDES_CONTROL_3 this weekend;
    The algorithm is base on my previous attachment, and loop the CTRL_3 value from 0x0 to 0xFFFF,
    keep HS_SERDES_CONTROL_2 as 0xe888, If it is able to link up, then we try it again.
    If the value is good and stable, it must jump into infinite loop w/ good value.

    The result shows we only have 0x4291 and 0x43f2 link up 4 times. The others are less than 4 times or no link up.
    It seems we are going to a wrong debug direction...

    We will try the same algorithm but removing the steps related to configure 'magic register' on init seq and using default value (0xa848) on HS_SERDES_CONTROL_2 today.
    Will let you know the result soon.

    If you have any advise, please let us know.

    Thank you.
    Alan
  • one more question,

    Do you think it would help
    if we write a state machine to toggle LT_TRAIN_CONTROL register 1.0x96 bit[0] and poll LT_TRAIN_STATUS register 1.0x97
    right after the 3 seq : 'init seq' + '1g-kx setting' + 'setup loopback on same port' ?

    Thank you.
    Alan
  • Alan,

    I do not advise using LT with the internal loopback mode of the device. Instead try HS_AGCCTRL[1:0] = 0x4 instead of HS_AGCCTRL[1:0] = 0x8. This may have affected your tuning of HS_SERDES_CONTROL_3. 

  • Hi, Malik, 

    We found some values of CTL_2 and CTL_3 are able to get link up, but failed on 2nd time easily.

    Later on we found adding delay after each configure stage is able to get link up without change CTL_2 and CTL_3 value, but it needs retry many times. 

    for example:

    RETRY with { [ 'Init seq' + DELAY + '1G-KX setting' + DELAY +  'set same channel HS input (0x1E.0x18  |= 0x4000)' + DELAY + 'setup deep remote loopback ' + DELAY  ] break if link up } 

    The DELAY cannot be less than 96 ms and also cannot large than 120 ms, otherwise it cannot link up even with retry. 

    The RETRY range is 1-60 times for overnight testing.  (60 times.. This is not acceptable..)

    If it is 10G-KR, we don't need these 'DELAY and 1G-KX setting then poll Intel backplane eth port status for link up.  

    Do you have any suggestion? is it possible 1G SI between Intel and TLK is not good? 

    Thank you.

    Alan

  • Alan,

    I am still looking into your issue but have not found a complete solution as of yet. I will update you when I have something more concrete. 

  • Hi, Malik,

    Thanks for update.
    Please let us know if there is anything worth to try.


    Thank you.
    Alan
  • Alan,

    Sorry for the late response. I have note been able to replicate or find similar issues to yours. The SI of the 1G-KX may be the issue here. Are there any differences in implementation between the 1G-KX and 10G-KR links in terms of trace length, cables or connector?
  • Malik,

    It's a typo for 'note' -> 'not' right?
    Is this mean you are able to get link up using TLK10232 with Intel X550 series backplane for both 1G-KX and 10G-KR?

    Since TLK10232 is connected to backplane, the connection environment must be the same between 10G-KR and 1G-KX.
    Unless x552 divide 1G and 10G to the different route.

    Thank you.
    Alan
  • Alan,

    Sorry for the late reply. Yes that was a typo. I did not use your specific backplane when running my simple test. My leading suspicion is that the SI between the TLK10232 and Intel X550 is not good. Just to be clear you are still not able to get a reliable link up when testing in deep remote loopback correct? Have you tried adding a data path reset in your testing algorithm? For example:

    RETRY with { [ 'Init seq' + DELAY + '1G-KX setting' + DELAY + 'set same channel HS input (0x1E.0x18 |= 0x4000)' + Data path reset + 'setup deep remote loopback ' + DELAY ] break if link up }
  • Hi, Malik, 

    We still not get reliable link up yet. 

    For data path reset, we already do it before 'set same channel HS input' :  

    RETRY with { [ 'Init seq' + DELAY + '1G-KX setting' + DELAY + Data path reset + 'set same channel HS input (0x1E.0x18 |= 0x4000)' + 'setup deep remote loopback ' + DELAY ] break if link up }

    Compare with your suggestion, which is put data path reset after 'set same channel HS input' :

    RETRY with { [ 'Init seq' + DELAY + '1G-KX setting' + DELAY + 'set same channel HS input (0x1E.0x18 |= 0x4000)' + Data path reset + 'setup deep remote loopback ' + DELAY ] break if link up }

    Just move the data path reset as yours, it seems not help.  

    For SI signal measurement, do you have any suggestion?

    The HW team is busy on the other stuffs, and the other modules are able to get link up on 1G with Intel backplane,

    they are not yet to debug in detail. 

    Thank you.

    Alan 

  • Alan,

    I will look into the config sequence further. Could provide the value for status registers listed below during your test? To evaluate your signal integrity a eye diagram could be generated using the test pattern generator internal to TLK10232 to generate a PRBS pattern and a high speed scope using a high impedance probe. You could also measure nominal (link up) data output and compare to a case where is link is not achieved. Also, please remind me if you are using a loopback test to help configure the TLK10232?

    • HS_ERROR_COUNTER
    • LS_LNx_ERROR_COUNTER
    • CHANNEL_STATUS_1
    • LS_STATUS_1
    • HS_STATUS_1
    • DATA_SWITCH_STATUS

  • Hi, Malik, 

    Yes, after init setting and enable loopback, we check the CPU eth port links status, if link up, we generate packets for loopback test. 

    So far 10G is able to get link up on host eth port but 1G doesn't. 

    For generate PRBS pattern, do I need to prepare some tools? or we can do it by configure TLK10232 registers. 

    The attachment is the log for both 10G and 1G status registers.

    Thank you.

    Alan

    TLK10322_10G_and_1G_setting_then_dump_status_reg.txt
    For 10G loopback, before sending packet, the status registers are: 
    
    HS_ERROR_COUNTER                     (0x10), data: 0xFFFD.
    LS_LN0_ERROR_COUNTER                 (0x11), data: 0xFFFD.
    LS_LN1_ERROR_COUNTER                 (0x12), data: 0xFFFD.
    LS_LN2_ERROR_COUNTER                 (0x13), data: 0xFFFD.
    LS_LN3_ERROR_COUNTER                 (0x14), data: 0xFFFD.
    CHANNEL_STATUS_1                     (0x0F), data: 0x0000.
    LS_STATUS_1                          (0x15), data: 0x8008.
    HS_STATUS_1                          (0x16), data: 0xC000.
    DATA_SWITCH_STATUS                   (0x1B), data: 0x0000.
    
    
    For 10 loopback, before sending packet, the status registers are (retry 10):
    
    ==1st==
    HS_ERROR_COUNTER                     (0x10), data: 0xFFFF.
    LS_LN0_ERROR_COUNTER                 (0x11), data: 0xFFFF.
    LS_LN1_ERROR_COUNTER                 (0x12), data: 0xFFFD.
    LS_LN2_ERROR_COUNTER                 (0x13), data: 0xFFFD.
    LS_LN3_ERROR_COUNTER                 (0x14), data: 0xFFFD.
    CHANNEL_STATUS_1                     (0x0F), data: 0x0150.
    LS_STATUS_1                          (0x15), data: 0x8801.
    HS_STATUS_1                          (0x16), data: 0xC005.
    DATA_SWITCH_STATUS                   (0x1B), data: 0x1020.
    
    ==2nd==
    HS_ERROR_COUNTER                     (0x10), data: 0xFFFF.
    LS_LN0_ERROR_COUNTER                 (0x11), data: 0xFFFF.
    LS_LN1_ERROR_COUNTER                 (0x12), data: 0xFFFD.
    LS_LN2_ERROR_COUNTER                 (0x13), data: 0xFFFD.
    LS_LN3_ERROR_COUNTER                 (0x14), data: 0xFFFD.
    CHANNEL_STATUS_1                     (0x0F), data: 0x0150.
    LS_STATUS_1                          (0x15), data: 0x8800.
    HS_STATUS_1                          (0x16), data: 0xC013.
    DATA_SWITCH_STATUS                   (0x1B), data: 0x1020.
    
    ==3rd==
    HS_ERROR_COUNTER                     (0x10), data: 0xFFFF.
    LS_LN0_ERROR_COUNTER                 (0x11), data: 0xFFFF.
    LS_LN1_ERROR_COUNTER                 (0x12), data: 0xFFFD.
    LS_LN2_ERROR_COUNTER                 (0x13), data: 0xFFFD.
    LS_LN3_ERROR_COUNTER                 (0x14), data: 0xFFFD.
    CHANNEL_STATUS_1                     (0x0F), data: 0x0150.
    LS_STATUS_1                          (0x15), data: 0x8806.
    HS_STATUS_1                          (0x16), data: 0xC005.
    DATA_SWITCH_STATUS                   (0x1B), data: 0x1020.
    
    ==4th==
    HS_ERROR_COUNTER                     (0x10), data: 0xFFFF.
    LS_LN0_ERROR_COUNTER                 (0x11), data: 0xFFFF.
    LS_LN1_ERROR_COUNTER                 (0x12), data: 0xFFFD.
    LS_LN2_ERROR_COUNTER                 (0x13), data: 0xFFFD.
    LS_LN3_ERROR_COUNTER                 (0x14), data: 0xFFFD.
    CHANNEL_STATUS_1                     (0x0F), data: 0x0150.
    LS_STATUS_1                          (0x15), data: 0x8806.
    HS_STATUS_1                          (0x16), data: 0xC010.
    DATA_SWITCH_STATUS                   (0x1B), data: 0x1020.
    
    ==5th==
    HS_ERROR_COUNTER                     (0x10), data: 0xFFFF.
    LS_LN0_ERROR_COUNTER                 (0x11), data: 0xFFFF.
    LS_LN1_ERROR_COUNTER                 (0x12), data: 0xFFFD.
    LS_LN2_ERROR_COUNTER                 (0x13), data: 0xFFFD.
    LS_LN3_ERROR_COUNTER                 (0x14), data: 0xFFFD.
    CHANNEL_STATUS_1                     (0x0F), data: 0x0150.
    LS_STATUS_1                          (0x15), data: 0x8882.
    HS_STATUS_1                          (0x16), data: 0xC009.
    DATA_SWITCH_STATUS                   (0x1B), data: 0x1020.
    
    ==6th==
    HS_ERROR_COUNTER                     (0x10), data: 0xFFFF.
    LS_LN0_ERROR_COUNTER                 (0x11), data: 0xFFFF.
    LS_LN1_ERROR_COUNTER                 (0x12), data: 0xFFFD.
    LS_LN2_ERROR_COUNTER                 (0x13), data: 0xFFFD.
    LS_LN3_ERROR_COUNTER                 (0x14), data: 0xFFFD.
    CHANNEL_STATUS_1                     (0x0F), data: 0x0150.
    LS_STATUS_1                          (0x15), data: 0x8804.
    HS_STATUS_1                          (0x16), data: 0xC011.
    DATA_SWITCH_STATUS                   (0x1B), data: 0x1020.
    
    ==7th==
    HS_ERROR_COUNTER                     (0x10), data: 0xFFFF.
    LS_LN0_ERROR_COUNTER                 (0x11), data: 0xFFFF.
    LS_LN1_ERROR_COUNTER                 (0x12), data: 0xFFFD.
    LS_LN2_ERROR_COUNTER                 (0x13), data: 0xFFFD.
    LS_LN3_ERROR_COUNTER                 (0x14), data: 0xFFFD.
    CHANNEL_STATUS_1                     (0x0F), data: 0x0150.
    LS_STATUS_1                          (0x15), data: 0x8822.
    HS_STATUS_1                          (0x16), data: 0xC011.
    DATA_SWITCH_STATUS                   (0x1B), data: 0x1020.
    
    ==8th==
    HS_ERROR_COUNTER                     (0x10), data: 0xFFFF.
    LS_LN0_ERROR_COUNTER                 (0x11), data: 0xFFFF.
    LS_LN1_ERROR_COUNTER                 (0x12), data: 0xFFFD.
    LS_LN2_ERROR_COUNTER                 (0x13), data: 0xFFFD.
    LS_LN3_ERROR_COUNTER                 (0x14), data: 0xFFFD.
    CHANNEL_STATUS_1                     (0x0F), data: 0x0150.
    LS_STATUS_1                          (0x15), data: 0x8800.
    HS_STATUS_1                          (0x16), data: 0xC001.
    DATA_SWITCH_STATUS                   (0x1B), data: 0x1020.
    
    ==9th==
    HS_ERROR_COUNTER                     (0x10), data: 0xFFFF.
    LS_LN0_ERROR_COUNTER                 (0x11), data: 0xFFFF.
    LS_LN1_ERROR_COUNTER                 (0x12), data: 0xFFFD.
    LS_LN2_ERROR_COUNTER                 (0x13), data: 0xFFFD.
    LS_LN3_ERROR_COUNTER                 (0x14), data: 0xFFFD.
    CHANNEL_STATUS_1                     (0x0F), data: 0x0150.
    LS_STATUS_1                          (0x15), data: 0x8803.
    HS_STATUS_1                          (0x16), data: 0xC003.
    DATA_SWITCH_STATUS                   (0x1B), data: 0x1020.
    
    ==10th==
    HS_ERROR_COUNTER                     (0x10), data: 0xFFFF.
    LS_LN0_ERROR_COUNTER                 (0x11), data: 0xFFFF.
    LS_LN1_ERROR_COUNTER                 (0x12), data: 0xFFFD.
    LS_LN2_ERROR_COUNTER                 (0x13), data: 0xFFFD.
    LS_LN3_ERROR_COUNTER                 (0x14), data: 0xFFFD.
    CHANNEL_STATUS_1                     (0x0F), data: 0x0150.
    LS_STATUS_1                          (0x15), data: 0x8822.
    HS_STATUS_1                          (0x16), data: 0xC012.
    DATA_SWITCH_STATUS                   (0x1B), data: 0x1020.
    
    

  • Alan Peng,

    Sorry for the late reply. I am currently looking into some design files to understand why you may be seeing this error. I will get back to you as soon as possible with potential solutions.

    TLK10232 can generate internal patterns to test connections. Please see section 3.17 10GBASE-KR Test Pattern Support of datasheet for more information.
  • Alan Peng,

    After some digging it seems to be multiple issues. First lets tackle some lane alignment issues as well as the LS and HS PLLs have not locked. Please make sure that you are applying the appropriate REFCLK signal for the 1G-KX link and that the appropriate REFCLK is selected in software, ensure clock dividers settings are correct as well. Also the file attached only has registers for "10G Loopback" should there be additional lines for 1G-KX or is this a typo (top line)?
  • Hi Malik, 

    Thanks for update. 

    Based on your description, we have following issues:

    1. Lane alignment issue
    2. LS and HS PLL have not locked. 

    Check HW and SW portions :

    1. REFCLK signal for 1G-KX
    2. Clock dividers setting for 1G-KX

    And yes, there is an typo on previous attachment. For retry portion, "10" -> "1G"; the retry portions are the log for 1G-KX retry; the first portion is the log for 10G-KR. 

    Will pass these info to HW and ask them for check reference clock portion first. 


    Thank you.

    Alan

  • Malik,

    Checking the schematic, the REFCLK is using 156.26MHz; after 1G setting and enable loopback, 1e.1d = 0. (bit [13:12] = 0 )
    Both HW and SW are using 156.25MHz.
    Is there any other register that you suggest to check ?

    If you shared your mail to us, then I can asked HW guy to send the schematic for you to review.

    Thank you.
    Alan
  • Alan,

    CLK_CONTROL, REFCLK_SW_SEL,LS_REFCLK_SEL should be checked and make sure that they align with HW selection for channel B. SW_PCS_SEL should be checked to make sure you are in !G-KX mode and check "Table 2-3. TLK10232 Operating Mode Selection" and "Table 4-1. Specific Line Rate and Reference Clock Selection for the 1GBASE-KX Mode" to ensure the proper HW and SW selections are made for your applications. Please private message me through E2E if you would like me to review your schematic.

  • Malik, 

    The attachment is the register dump for most of registers on TLK10232 datasheet. 

    After you accept the invitation of friendship, then I can send you the schematic. 

    TLK10232_reg_dump_after_1G_lpbk_setting_channael_a.txt
    enter TestCard TLK10232 Utilities item > h
    
    Port0 (Channel A) addr is 0xA; Port1 (Channel B) addr is 0xB
    
    Enter addr [0x0]:  a
    
    SMI addr is : 10
    
    [1] Vendor Specific Device register.
    [2] PMA/PMD register.
    [3] PCS register.
    [4] Auto-Negotiation register.
    [5] User Define register.
    Enter Device Type you want to read: [1]:  1
    vendor specific registers
    0x1e reg 0x0 = 0x610
    0x1e reg 0x1 = 0x3a8
    0x1e reg 0x2 = 0x831d
    0x1e reg 0x3 = 0xe888
    0x1e reg 0x4 = 0x5252
    0x1e reg 0x5 = 0x2000
    0x1e reg 0x6 = 0xf115
    0x1e reg 0x7 = 0x0
    0x1e reg 0x8 = 0x0
    0x1e reg 0x9 = 0x380
    0x1e reg 0xa = 0x4000
    0x1e reg 0xb = 0xd18
    0x1e reg 0xc = 0x332
    0x1e reg 0xd = 0x2f80
    0x1e reg 0xe = 0x0
    0x1e reg 0xf = 0x150
    0x1e reg 0x10 = 0xffff
    0x1e reg 0x11 = 0xffff
    0x1e reg 0x12 = 0xfffd
    0x1e reg 0x13 = 0xfffd
    0x1e reg 0x14 = 0xfffd
    0x1e reg 0x15 = 0x8805
    0x1e reg 0x16 = 0xc002
    0x1e reg 0x17 = 0x2000
    0x1e reg 0x18 = 0x4c20
    0x1e reg 0x19 = 0x2500
    0x1e reg 0x1a = 0x4c20
    0x1e reg 0x1b = 0x1820
    0x1e reg 0x1c = 0x0
    0x1e reg 0x1d = 0x0
    0x1e reg 0x1e = 0x0
    0x1e reg 0x1f = 0x0
    0x1e reg 0x8000 = 0x4c0
    0x1e reg 0x8001 = 0x207
    0x1e reg 0x8002 = 0x2fe
    0x1e reg 0x8003 = 0x283
    0x1e reg 0x8004 = 0x17c
    0x1e reg 0x8021 = 0xf
    0x1e reg 0x8022 = 0x0
    0x1e reg 0x8023 = 0x0
    0x1e reg 0x8024 = 0x0
    0x1e reg 0x8025 = 0xf000
    0x1e reg 0x8026 = 0x0
    0x1e reg 0x8027 = 0x0
    0x1e reg 0x8028 = 0x0
    0x1e reg 0x8029 = 0x0
    0x1e reg 0x802a = 0x2fd
    0x1e reg 0x802b = 0x2fd
    0x1e reg 0x802c = 0x207
    0x1e reg 0x802d = 0x2fd
    0x1e reg 0x802e = 0x2fd
    0x1e reg 0x802f = 0x207
    0x1e reg 0x8040 = 0x0
    0x1e reg 0x8041 = 0x0
    0x1e reg 0x8100 = 0x1
    0x1e reg 0x8101 = 0x4
    
    enter TestCard TLK10232 Utilities item >  h
    
    Port0 (Channel A) addr is 0xA; Port1 (Channel B) addr is 0xB
    
    Enter addr [0x0]:  a
    
    SMI addr is : 10
    
    [1] Vendor Specific Device register.
    [2] PMA/PMD register.
    [3] PCS register.
    [4] Auto-Negotiation register.
    [5] User Define register.
    Enter Device Type you want to read: [1]:  2
    pma/pmd registers
    0x1 reg 0x0 = 0x0
    0x1 reg 0x1 = 0x82
    0x1 reg 0x2 = 0x4000
    0x1 reg 0x3 = 0x5100
    0x1 reg 0x4 = 0x11
    0x1 reg 0x5 = 0xb
    0x1 reg 0x6 = 0x4000
    0x1 reg 0x7 = 0x0
    0x1 reg 0x8 = 0xb000
    0x1 reg 0x9 = 0x0
    0x1 reg 0xa = 0x1
    0x1 reg 0xb = 0x50
    0x1 reg 0xc = 0x0
    0x1 reg 0xd = 0x0
    0x1 reg 0xe = 0x0
    0x1 reg 0xf = 0x0
    0x1 reg 0x96 = 0x2
    0x1 reg 0x97 = 0x0
    0x1 reg 0x98 = 0x0
    0x1 reg 0x99 = 0x0
    0x1 reg 0x9a = 0x0
    0x1 reg 0x9b = 0x0
    0x1 reg 0x9c = 0x0
    0x1 reg 0x9d = 0x0
    0x1 reg 0x9e = 0x0
    0x1 reg 0x9f = 0x0
    0x1 reg 0xa0 = 0x0
    0x1 reg 0xa1 = 0x3c01
    0x1 reg 0xa2 = 0x0
    0x1 reg 0xa3 = 0x0
    0x1 reg 0xa4 = 0x0
    0x1 reg 0xa5 = 0x0
    0x1 reg 0xa6 = 0x0
    0x1 reg 0xa7 = 0x0
    0x1 reg 0xa8 = 0x0
    0x1 reg 0xa9 = 0x0
    0x1 reg 0xaa = 0x3
    0x1 reg 0xab = 0x1
    0x1 reg 0xac = 0x0
    0x1 reg 0xad = 0x0
    0x1 reg 0xae = 0x0
    0x1 reg 0xaf = 0x0
    0x1 reg 0x8001 = 0xcc4c
    0x1 reg 0x8002 = 0x0
    0x1 reg 0x8003 = 0x0
    0x1 reg 0x8004 = 0x0
    0x1 reg 0x8005 = 0xce00
    0x1 reg 0x8006 = 0x0
    0x1 reg 0x8007 = 0x0
    0x1 reg 0x8008 = 0x80
    0x1 reg 0x8009 = 0x0
    0x1 reg 0x800a = 0x0
    0x1 reg 0x800b = 0x0
    0x1 reg 0x800c = 0x0
    0x1 reg 0x800d = 0x0
    0x1 reg 0x800e = 0x0
    0x1 reg 0x800f = 0x0
    0x1 reg 0x8010 = 0xfffd
    0x1 reg 0x8011 = 0xfffd
    0x1 reg 0x8012 = 0xfffd
    0x1 reg 0x8013 = 0xfffd
    0x1 reg 0x8014 = 0xfffd
    0x1 reg 0x8015 = 0xfffd
    0x1 reg 0x8016 = 0xfffd
    0x1 reg 0x8017 = 0xfffd
    0x1 reg 0x8018 = 0x0
    0x1 reg 0x8019 = 0xffff
    0x1 reg 0x801a = 0xffff
    0x1 reg 0x801b = 0xffff
    0x1 reg 0x801c = 0xffff
    0x1 reg 0x801d = 0xffff
    0x1 reg 0x801e = 0xffff
    0x1 reg 0x801f = 0xffff
    0x1 reg 0x9001 = 0x200
    0x1 reg 0x9002 = 0x1335
    0x1 reg 0x9003 = 0x5e29
    
    enter TestCard TLK10232 Utilities item > h
    
    Port0 (Channel A) addr is 0xA; Port1 (Channel B) addr is 0xB
    
    Enter addr [0x0]:  a
    
    SMI addr is : 10
    
    [1] Vendor Specific Device register.
    [2] PMA/PMD register.
    [3] PCS register.
    [4] Auto-Negotiation register.
    [5] User Define register.
    Enter Device Type you want to read: [1]:  3
    pcs registers
    0x3 reg 0x0 = 0x0
    0x3 reg 0x1 = 0x82
    0x3 reg 0x8 = 0x8001
    0x3 reg 0x20 = 0x1005
    0x3 reg 0x21 = 0x0
    0x3 reg 0x22 = 0x0
    0x3 reg 0x23 = 0x0
    0x3 reg 0x24 = 0x0
    0x3 reg 0x25 = 0x0
    0x3 reg 0x26 = 0x0
    0x3 reg 0x27 = 0x0
    0x3 reg 0x28 = 0x0
    0x3 reg 0x29 = 0x0
    0x3 reg 0x2a = 0x0
    0x3 reg 0x2b = 0x0
    0x3 reg 0x2c = 0x0
    0x3 reg 0x2d = 0x0
    0x3 reg 0x2e = 0x0
    0x3 reg 0x2f = 0x0
    0x3 reg 0x8000 = 0xb0
    0x3 reg 0x8010 = 0xfd
    
    enter TestCard TLK10232 Utilities item > h
    
    Port0 (Channel A) addr is 0xA; Port1 (Channel B) addr is 0xB
    
    Enter addr [0x0]:  a
    
    SMI addr is : 10
    
    [1] Vendor Specific Device register.
    [2] PMA/PMD register.
    [3] PCS register.
    [4] Auto-Negotiation register.
    [5] User Define register.
    Enter Device Type you want to read: [1]:  4
    auto neg registers
    0x7 reg 0x0 = 0x2000
    0x7 reg 0x1 = 0x98
    0x7 reg 0x2 = 0x4000
    0x7 reg 0x3 = 0x5100
    0x7 reg 0x4 = 0x0
    0x7 reg 0x5 = 0x80
    0x7 reg 0x6 = 0x0
    0x7 reg 0x7 = 0x0
    0x7 reg 0x8 = 0x0
    0x7 reg 0x9 = 0x0
    0x7 reg 0xa = 0x0
    0x7 reg 0xb = 0x0
    0x7 reg 0xc = 0x0
    0x7 reg 0xd = 0x0
    0x7 reg 0xe = 0x0
    0x7 reg 0xf = 0x0
    0x7 reg 0x10 = 0x1001
    0x7 reg 0x11 = 0x80
    0x7 reg 0x12 = 0xc000
    0x7 reg 0x13 = 0x1
    0x7 reg 0x14 = 0x0
    0x7 reg 0x15 = 0x0
    0x7 reg 0x16 = 0x2000
    0x7 reg 0x17 = 0x0
    0x7 reg 0x18 = 0x0
    0x7 reg 0x19 = 0x0
    0x7 reg 0x1a = 0x0
    0x7 reg 0x1b = 0x0
    0x7 reg 0x1c = 0x0
    0x7 reg 0x1d = 0x0
    0x7 reg 0x1e = 0x0
    0x7 reg 0x30 = 0x3
    
    enter TestCard TLK10232 Utilities item >

    Thank you.

    Alan

  • Alan,

    Sorry for the delay, I am still looking into the material you have sent. I am still reviewing your documents looking for possible issues and will get back to you as soon as possible.
  • Malik,

    Thanks for update. Just sent you a private message for reviewing schematic.
    Please review it once you have time.

    Thank you.
    Alan
  • Alan,

    Is there any more support needed for this issue?
  • Hi Malik, 

    Glad to see you come back.

    Yes, we still need your support for review the schematic and the register dump log. 

    Please advise. 

    Thank you.

    Alan

  • Alan,

    On my first pass through your schematic I did not see anything that would allow for intermittent connection of the 1G-KX link. You are only using REFCLK0 in this design, correct? Also the 1G-KX link is on Channel A or B? going through the most recent reg dump file it seems that the configurations are only for Channel A which is the 10G-KR link (per the original post). Please correct me if I am wrong. Could you try the two suggestions below and let me know if your test results improve?

    1. For the 1G-KX link only could you try 0x1e.0x9000= 0x0245? If you would like to continue using AN.

    2. If #1 does not work, completely disable AN and LT and then configure Channel B for 1G-KX link? (0x1e.0x96 = 0x0000) In the "TLK10232_settings.docx" you disable and re-enable this feature before setting 1G-KR mode, correct?
  • Malik, 

    Yes, only REFCLK0 in this designed. will double confirm with HW team later. 

    Both Channel A and B are designed as the same architecture. They are connected to CPU x552 interfaces. 

    Since x552 is supporting both 10G and 1G, we need to bring up these 2 speeds on TLK10232. 

    This is why the log only configure Channel A.

    (Actually I also try to get link up on Channel B for 1G, but the result is the same as Channel A)

    Case 1: 

    Using "TI init setting" + "0x1e.9000 = 0x0245" + "set path to SAME_HS_INPUT", the ethtool show link up on 10G. 

    Case 2: 

    If we disable AN and LT, which is "TI init setting" +"0x1e.9000 = 0x0245"  + "0x1e.0x96 = 0 " + "set path to SAME_HS_INPUT", the ethtool shows no link. 

    For Case 1, I think the result is due to LT and AN are working, the speed is train to 10G. 

    Do you think it is possible that it is 1G but ethtool polling wrong status register and shows it is 10G? 

    On TLK10232_setting.docx, for "init seq", we does disable AN and LT, then enable them; later on we disable AN on "1G-KX setting".

    Otherwise it will train to 10G, right? 

    Thank you.

    Alan

  • Alan,

    I am unsure of the ethtool and what status registers it is polling, Is this the result in the latest reg dump? Please confirm my understanding, you would like both 10G and 1G mode enabled for both Channel A and Channel B? You would like TLK10232 to change modes (10G and 1G) to match the mode of x552? I am trying to understand if the speeds are fixed on on each channel (i.e. Channel A = 10G & Channel B = 1G only).

    Can you confirm that when you try to bring up 1G link that x552 is in its 1G mode? In other words, is x552 only in 10G mode when testing? 

  • Alan,

    Is there any more support needed for this issue? If so please reply with any relevant details so that I can further assist you. For now I will be marking this thread as "TI Thinks Resolved". If you have resolved your issue, please post the solution to the original problem/post for others with similar issues.
  • Malik, 

    Just come back from Holiday. 

    Please see inline comment with 'Alan' below: 

    I am unsure of the ethtool and what status registers it is polling, Is this the result in the latest reg dump? 

    [Alan] : my experiment on using '0x1e.0x9000= 0x0245' which set TLK10232 link with 1G and AN enabled, but the ethtool shows the link status is link up on 10G.

    The result must be 2 cases :

    a. the speed is trained to 10G by AN.

    b. the ethtool is polling wrong status register on TLK, it shows link up on 10G but the speed may be 1G actually.  

    We used bit 1 @0x7.0x30 for check link. Do you have suggestion for the other register to check current link speed on TLK10232?  

    Please confirm my understanding, you would like both 10G and 1G mode enabled for both Channel A and Channel B?

    [Alan] : Yes. For both Channel A and Channel B, we want to use TLK10232 to link up on 1G and doing loopback, switch to 10G and doing loopback again. 

    The purpose is checking product link ability for both 1G and 10G. 

    You would like TLK10232 to change modes (10G and 1G) to match the mode of x552? I am trying to understand if the speeds are fixed on on each channel (i.e. Channel A = 10G & Channel B = 1G only).\

    [Alan] : Yes. The mode of x552 is compatible with both 10G and 1G with AN enabled as default. It should be able to link up with TLK10232 for both 1G and 10G.   

    Can you confirm that when you try to bring up 1G link that x552 is in its 1G mode? In other words, is x552 only in 10G mode when testing? 

    [Alan] : The mode on x552 is decided by Intel LEK, it is similar to a kink of FW, we are sure that x552 is able to get link up to 1G with the other link partner. 

    Thank you.

    Alan

  • Hi Alan,

    Sorry for the late reply. In general it is best to have auto negotiation enabled for your desired operation. 0x7.0x30 is the status register to be checked for link mode status when Auto-negotiation is enabled.I believe that the link is still auto training to 10G. Is it possible for you to probe the high speed link?

  • Hi, Malik,

    Thanks for your help, and there is another TI FAE, Cassidy Aarstad, also contacted me by my mail.

    We are able to get link up on 1G with AN on, all we have to do is add additional setting on '1G-KX setting' (TLK10232_setting.docx):
    register 7.0x11 = 0x20.

    Later on we are able to link up with 1G, it is verified with ethtool.

    Thanks for your help and keep follow up this thread.
    And thanks for Cassidy who also follow up and share the document with us.

    Alan