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DP83867IR: Auto negotiation and network communication issues

Part Number: DP83867IR

Hi,

We are designing a bronchoscope with DP83867IR as Ethernet Phy.This is a Xilinx xc7z02 FPGA based design We are facing some issues with it.Details are given below

1. Auto negotiation is not taking place.

2. We tried to check for pulse transaction in the output data lines we were not able to see any transactions.

3. We see that MDIO communication is taking place properly.

4. We came to know that same IC is being used in ZCU102 and cross verified the schematics.

Is there any special PCB routing design to be adopted?

I have attached the schematics for your reference 

Please help us out.

  • Hi Nishitha,

    I have some follow up questions for better understanding the system.

    1. What is the value and tolerance of the RBIAS resistor (R22) used here?
    2. Can you share the strap resistor settings?
    3. Read back values from the following register and share the values.
    0x00, 0x01, 0x04, 0x09, 0x10, 0x11, 0x1E, 0x6E, 0x6F.
    4. What is the cable type and cable length?
    5. What is the link partner?
    6. The decoupling capacitors on the supply pins do not meet the datasheet requirement. Each supply pin needs 2 capacitors.

    -Regards,
    Aniruddha
  • Hi Aniruddha,

    Sorry for late reply, here is the answer for your questions

    1.RBIAS resistor value is 11K 1% tolerant

    2.We didn't use any resistor strapping

    3.The values of those registers are
    Value of Reg 0 is 0x1140

    Value of Reg 1 is 0x7949

    Value of Reg 4 is 0xDE1

    Value of Reg 9 is 0x1300

    Value of Reg 0x10 is 0x5048

    Value of Reg 0x11 is 0x2

    Value of Reg 0x1E is 0x2

    Value of Reg 0x6E is 0x31

    Value of Reg 0x6F is 0x3000
    4.CAT-6 cable of length 2 metres is being used

    5.Link partner is my PC.

    6.Our MDIO communication is proper.So is this question still valid?

  • Hi Nishtha,

    From register 0x9, it looks like you are forcing DP83867 in Forced Gigabit slave. This can possibly create contention with link partner. Can you try with disabling force slave and leave it in auto Master/Slave mode?
    Since you are not using strap resistor have you implemented the software as per the Note on Page 48 of the datasheet regarding RX_CTRL. RX_CTRL needs to be strapped in mode 3. If it cannot be strapped in mode 3 then bit 7 of register 0x31 needs to be cleared.
    For decoupling caps, I will recommend to use values mentioned in the datasheet. Proper decoupling is needed not only for MDIO communication but for overall proper operation of the PHY.

    -Regards,
    Aniruddha
  • Hi Aniruddha,

    I tried to clear clear bit 12 of register 9 and enable auto negotiation in software,but still auto negotiation doesn't take place.

    I doubted the hardware and gone through layout files.I found out that data lines were not length matched.I have attached the details of length

    Here I can see that the output of Phy differential pairs are length matched only inside the pair but not among the pairs i.e.Eth_Md1_n and Eth_md1_p are length matched but Eth_Md1 and Eth_Md2 are not length matched.

    I have few questions

    1. Is it necessary to length match  among Eth_md1 - Eth_md4 ?

     What is it's impact on auto negotiation part? Is my device unable to perform auto negotiation because of this?

    2.The Ethernet data lines (the lines between my Phy and FPGA) should be length matched right?

    This doesn't have anything to do with auto negotiation part right?

  • We are waiting for your reply. Thank you

  • Hi,

    Let me try to help here since Aniruddha is out of office.

    The MDI pairs should be length matched. Your design has more than 500mil difference between MDI_1 and MDI_2 pairs, which will affect the performance for sure.

    However, not having link over 2m cable could be caused by something else.

    If you do not have any strap resistor on the board, DP83867 is strapped into a "Not Applicable" mode. The most critical strap pin is RX_DV/RX_CTRL pin. It must be strapped to Mode 3 for proper operation.

    Regards,

    Hung Nguyen

  • Hi,

              We have already tried strapping the mode pin but it didn't solve our issue.We are designing second version of our board.I am attaching schematics of this version.Can you please check the schematics and tell whether it's proper or not.Right now layout is in progress once it's completed we will share the layout files for your perusal

  • Hi I facing similar situation.

    In my case and also matches the advised change setting to strap 3 or strap 4 I use strap 4,  I'm getting reg 0x9 0x1300,( don;t now what you getting) when setting it manually to 0x300, master slave negotiation starts and link comes up. - but this is not described in TI datasheet so no guarantee... but seems to work in my case

    I'm  following this case cause I wonder what is the correct way.

    BTW my strap registers are 0x6e = 0x0085   and 0x6f 0x0100

    Regards

    Baruch

  • After some more investigation,

    Using RX_DV/RX_CTRL bootstarp mode 3  (and not 4)  vitrified by 0x6e   new val 0x05,  

    I recommend to verify the bootstrap mode with register 0x6e, since the resistors set can have some inaccuracy,

    You can try to tune register with voltmeter readings hold the PHY in reset mode, according to bootstarp mode table.

    Master slave is also set to negotiation enable, verified by register 0x9 new val 0x300

    Now link is up, without any bit banging .

    Most driver automatically and independently set speed duplex auto negotiation, this fact mask the issue boostarp 4 is not recommended!!!  

    The affect of bootstrap mode 3-4 on master/slave negotiation is unclear from pdf. seems that boot strap 3 enable master/slave negotiation as well.

    Regards

    Baruch