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DP83867E: After RESETn is cleared, MDIO bit goes Low and stays Low

Prodigy 140 points

Replies: 22

Views: 317

Part Number: DP83867E

Can't seem to figure out why device is unable to function properly..  Reviewed voltage levels and clock, all appear to be within datasheet parameters.  Replaced device with new one and still same results.  Any idea what would cause such behavior? 

  • Hi Darryn,

    Do you have a schematic?

    Problems with MDIO are usually related to improper strapping. GPIO_0 can often cause this issue. If GPIO_0 is placed in mode 2 or mode 4, MDIO will become unresponsive.

    Please try to isolate GPIO_0, or pull it down strongly to ground.

    Best Regards,

    Rob Rodrigues

    CTS (Clock & Timing Solutions) Systems Engineer

  • In reply to Rob Rodrigues:

    Thank you Rob for getting back to me.  I didn't see that in the data sheet as a potential problem.

  • In reply to Darryn Long:

    Hi Darryn,

    I see a few items you may want to verify and correct in your schematic if needed.

    1. RBIAS must be 11k 1%. The schematic says 2.49k. Maybe this is mismarked.
    2. The XI reference frequency to the PHY is always 25MHz. It appears maybe that the frequency is 125MHz on this line as per the net name.
    3. I don't see a pull-up resistor on MDIO, maybe it is off sheet. Please make sure there is 1 1.5k - 2.2k pull-up on MDIO net. MDIO is an open drain pin and needs a pull-up to VDDIO.

    Do you have a diagram of the LED circuit? 1.8V is a low voltage and your LEDs may not glow brightly due to the low voltage.

    Best Regards,

    Rob Rodrigues

    CTS (Clock & Timing Solutions) Systems Engineer

  • In reply to Rob Rodrigues:

    Thank you for your feedback Rob.

    RBIAS did have an incorrect resistor installed, but we caught that earlier.

    The 125MHz clock is a typo.  It is 25MHz.  

    We have three PHYs, so the 9k internal pulldown on each chip creates a 3k pull down on the signal line...correct?

  • In reply to Darryn Long:

  • In reply to Darryn Long:

    Hey Darryn,

    Thank you for sharing the extra pages of the schematics. I still do not see the LED circuit. I want to see all connections to the 1G_PORT0_1V8_LED_3 and 1G_PORT0_1V8_GPIO_1 nets.

    Best Regards,

    Rob Rodrigues

    CTS (Clock & Timing Solutions) Systems Engineer

  • In reply to Rob Rodrigues:

    Hi Rob,

    Those two signals are being routed to a CPLD (Altera Max5) device, which is being used as a voltage translator. (+1.8V --->+3.3V).

    Their outputs go to a connector where they are unused. I'd have to review the designer's code to see if they're being driven at all.

    We contracted out this design and I'm trying to figure out the problems and solve them, so I really appreciate your help!

  • In reply to Darryn Long:

    Hi Darryn,

    Can you probe those traces and hold the DP83867 in reset using the RESET_N signal? You should see 0V on those lines if you are in mode 1. Any voltage on those lines will cause the PHY to strap into an improper mode.

    If not, can you sever the traces anywhere physically on the board?

    Best Regards,

    Rob Rodrigues

    CTS (Clock & Timing Solutions) Systems Engineer

  • In reply to Darryn Long:

    Sorry Rob, I misread the schematic.

  • In reply to Darryn Long:

    Rob,

    I'll have to get that for you tomorrow.

    Thank you for your help.

    Darryn

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