• Resolved

DS90UB940-Q1: Is VGA @60 RGB565 possible with Internal TPG(Test Pattern Generator)?

Part Number: DS90UB940-Q1


I want to know if  RGB565 VGA output is possible by embedded TPG as following settings.

        // disable tpg
	DS90UB940WriteReg(0x65, 0x00); //Internal clock enable for TPG

	//DS90UB940WriteReg(0x37, 0x12); // 2data lane, 1csi active.

	// set timing
	DS90UB940WriteReg(0x66, 0x00); //Red sub pixel
	DS90UB940WriteReg(0x67, 0x00); //Red sub pixel
	DS90UB940WriteReg(0x66, 0x01); //Green sub pixel
	DS90UB940WriteReg(0x67, 0x00); //Green sub pixel
	DS90UB940WriteReg(0x66, 0x02); //Blue sub pixel
	DS90UB940WriteReg(0x67, 0x00); //Blue sub pixel
	DS90UB940WriteReg(0x66, 0x03); //Clock Divder for VGA @ 60
	DS90UB940WriteReg(0x67, 0x08); // 

	// H & V total : refer to VESA VGA

	DS90UB940WriteReg(0x66, 0x04); // H total(800, 0x320) LSB
	DS90UB940WriteReg(0x67, 0x20); //

	DS90UB940WriteReg(0x66, 0x05); // V & H total MSB
	DS90UB940WriteReg(0x67, 0xD3); //

	DS90UB940WriteReg(0x66, 0x06); // V total(525, 0x20D) LSB
	DS90UB940WriteReg(0x67, 0x20); //

	// set H sync

	DS90UB940WriteReg(0x66, 0x0A);
	DS90UB940WriteReg(0x67, 96);

	// set V sync
	DS90UB940WriteReg(0x66, 0x0B);
	DS90UB940WriteReg(0x67, 2);

	// set Hbp
	DS90UB940WriteReg(0x66, 0x0C);
	DS90UB940WriteReg(0x67, 48);

	// set Vbp
	DS90UB940WriteReg(0x66, 0x0D);
	DS90UB940WriteReg(0x67, 33);

	// H & V activ
	DS90UB940WriteReg(0x66, 0x07); // H actvie(640, 0x280) LSB
	DS90UB940WriteReg(0x67, 0x80); //
	DS90UB940WriteReg(0x66, 0x08); // V active LSB & H actvie MSB
	DS90UB940WriteReg(0x67, 0x02); //
	DS90UB940WriteReg(0x66, 0x09); // V actvie(480, 0x1E0) MSB
	DS90UB940WriteReg(0x67, 0x1E); //

	// set H(-) & V(-) pol
	DS90UB940WriteReg(0x66, 0x0E);
	DS90UB940WriteReg(0x67, 0x03); 
	DS90UB940WriteReg(0x6A, 0x20); // forced to 2 lane

	//set output format RGB565, RGB444
	DS90UB940WriteReg(0x6B, 0x20); //CSI-2 data type 0x22

        // set tpg
	DS90UB940WriteReg(0x64, 0x11); // white raster pattern
	DS90UB940WriteReg(0x65, 0x04); // select Internal clock enable for TPG