Dear Sirs
In the design reference TIDA-060017 Transmitting SPI Signals Over LVDS Interface Reference Design, section 2.3.1.2 Determining Maximum SPI Clock (SCLK) vs. Distance, Table 3 Timing Parameters, it says the time delays for devices SN65LVDS31, SN65LVDS33 and ADS8910B are 4ns, 3.5ns and 6.4ns respectively. I looked at the data sheets and could not see where these numbers came from. In addition, 5ns/m seems a little fast. For a typical FR4 material, I got 5.71ns/m. Please help me understand how these numbers were derived. Thank you for your time.