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DS90UB949-Q1: TMDS input pixel clock for valid display transmission

Part Number: DS90UB949-Q1

Hi!


My customer is reviewing SERDES with the following block

 H/U Side : H/U SoC -> (HDMI/TMDS) -> DS90UB949 => (Single FPD Link)=>DS90UB940 -> MIPI CSI-2 -> Cluster SoC

The Pixel clock demanded by the final Cluster SOC is the same as the calculation formula below and is 27.72Mhz.

Cluster BVM image display area: 720x480

Pixel Clock = (Include Blank) 880*525*30(FPS)*2 = 27.72MH


Considering the loss of SERDES,Can you advise how much of the TMDS Clock value we should input into the serializer from the headunit to send 27.72 Mhz on the Cluster SOC side.

Pleas check it.

Thank you

Best Regards.

From Anthony.

  • Hello,

    yes, this can work if the input PCLK is 27.72MHz. pls check 949's d/s, the input TMDS clock range is from 25MHz to 96MHz if single FPD-Link is selected.

    /////////////////////////////data rate description in 949 d/s, you also can get this parameter spec. in 949 d/s/////////////

    Feature Description (continued)
    The device supports TMDS clocks in the range of 25 MHz to 96 MHz over one lane, or 50 MHz to 170 MHz over
    two lanes. The FPD-Link III serial stream rate is 3.36 Gbps maximum (875 Mbps minimum), or 2.975 Gbps
    maximum per lane (875 Mbps minimum) when transmitting over both lanes.

    regards,

    Steven