Hi,
my customer sees performance on a RGMII lane, 80Mbit/s in a 100MBit/s use case is seen only.It's the fourth Eth interface used with a Layerscape processor.
Additional, they see a lot of reflections on the 2 SGMII lanes.
I need help in the following points:
- Help me find solutions/recommendations regarding schematic & layout, especially the decoulping
- Register data of the troubling Eth Phy:
ETH4:
SMI-Address 0x02
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
1140 7949 2000 A231 0DE1 0000 0064 2001 0000 0200 0000 0000 0000 401F 0077 3000
10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
4000 0002 0000 0040 29C7 0000 0000 0040 6150 4444 0002 0000 0000 0000 0002 0000
The block diagram, eye diagram is in a seperate emial chain.
Thank you, kind regards,
Marion