DP83822I: RX_CLK pulled low during reset

user448712

Part Number: DP83822I
Other Parts Discussed in Thread: AM3358, TLK105

I use DP83822 in design with AM3358 as PRU PHY.

In Datasheet page 8 is : During RESET: RX_CLK on pin 25 is output O with PD.

It means Output active LOW?

After the power up, this line is used to configure our Sitara.(LCD data 14) Therefore his circuitry did not work, because our device drives this pin to ground.

Is there any recommendation, how to overcome this behavior?

"After power up the system, our device pulls the pin 25 RX_CLK to low, even if my customer adds a 1kOhm pull up resistor to the line.

This is completely different to the behavior from our TLK105."

Best regards,

Jiri

over 4 years ago

0 Geet Modi over 4 years ago

TI__Mastermind 26320 points

Hi Jiri,

Which device powers up first ? PHY or Sitara ? What state you need this pin ? You can isolate this pin by using MII Isolate.

Regards,

Geet

0 user448712 over 4 years ago in reply to Geet Modi

Prodigy 30 points

Hi Geet,

As power chip is used TPS65217C PHY is powered from LDO4. Sitara starts after Power_good (PWRONRST), so PHY start first. PHY RST is GPIO but during RST is MII_RXCLK output active low.

MII Isolate is not usable because default is not isolated and for set to isolate I need boot Sitara. SYSBOOT is set for 19.2MHz and I need 24MHz (MII_RXCLK is LCD14).

Thanks,

Jiri

0 Geet Modi over 4 years ago in reply to user448712

TI__Mastermind 26320 points

Hi Jiri,

Can you try using IEEE Power Down thru PIN while PHY in reset ?

Regards,

Geet

0 user448712 over 4 years ago in reply to Geet Modi

Prodigy 30 points

Hi Geet,

Power down seems good, but it is not well documented in datasheet.

is somewere table like:

"Table 1. IO Pins State During Reset"

but about power down?

Regards,

Jiri

0 Geet Modi over 4 years ago in reply to user448712

TI__Mastermind 26320 points

Hi,

During Power Down : Output IOs will stop driving.

Regards,

Geet

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DP83822I: RX_CLK pulled low during reset