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TUSB1210: EMI concerns from USB and ULPI clock rates
Part Number: TUSB1210
I have very little control over the TUSB1210 USB PHY in terms of EMI/EMC. I am using a Xilinx ZYNQ device to communicate over ULPI running at 60 MHz. My customer is testing our board in their setup. They failed FCC Rule 15. I am asking the customer to just test Full Speed instead of High Speed to see if the problem areas move around relative to the USB data rate. Since I have very little control at this device level, I am looking for options that might help reduce the EMI/EMC. I didn't see any slew rate items in the memory map. I see in the datasheet in Section 4.1 (Datasheet revised August 2012) that the USB PLL generates both the 60 MHz ULPI and the USB data interface rate (480 Mbps). I use a 24 MHz clock from the FPGA to feed the TUSB1210.
you need to be very careful about layout of 60Mhz clk, it's better having ground shield of this clk.
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In reply to Brian Zhou:
That is a good point. We (my team) did EMI/EMC testing on the product ourselves when we first introduced it back in 2013. We didn't have a problem at that time. The board hasn't changed. I have asked our partner who is doing the testing to try a USB 1.1 Hub (for Full Speed) just to see how the EMI/EMC outputs change. I should hear something back from them in the next few days. In the mean time, I will look at the 60 MHz clock layout to see if this might be an influence. What would you be specifically looking for in your review of the 60 MHz clock?
In reply to Bill Whitehead:
pls check if 60Mhz clk passing though different power/gound layer, or close to DP/DM signal.
It looks like the 60 MHz clock gets routed down to Layer 7. That is also the layer that DM and DP get routed on. I am showing the top level from Altium and then just Layer 7 below. I don't see a problem with this.
My customer just got back to me. He said he tried a USB 1.1 Hub to get it to run at Full Speed (12 Mbps) and said nothing changed. What am I missing? He has two of our cameras and he told me both are exhibiting this same behavior. Could I have some type of "Lot" issue with either those boards or the USB PHY?
how about Vcc and gound layer?
Can you try 20 ohm on 60Mhz clk? it may help.
I don't have access to a series resistor to slow down the edge of the Clock. It is coming from a Xilinx ZYNQ device. I believe that the slew rate is already set to slow on that pin.
Also, there are other traces between these two on Layer 7. Layer 8 has some power planes, but there are different power planes over the two areas, one under the 60 MHz clock, and a different one under the USB DP/DM signals.
it seems this EMI issue caused by layout.
That was my guess, but wasn't sure. Could there be any manufacturing defect that might cause or influence the EMI issue? The USB PHY is working, so I don't have a short or open between the part and the Xilinx ZYNQ device. I believe the boards were cleaned after MFG, so I wouldn't expect flux or anything else to be present or cause an issue. Other thoughts?
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