Part Number: SN75DP130
We use the P/N SN75DP130DSRGZT (dual-supply) as a source re-driver. We do not do anything special with setting, all register values are default programming. The issue we have is that we can drive only some Dell monitors but not every Dell monitor we are able to find in our lab. Test set-up: 1080p60 output using a 6-ft long DP cable to 5 different Dell monitors with DP port, 3 models work OK and 2 not working, ie nothing shown on the screen and monitor go eventually to sleep mode). We keep the set-up identical and just swap Dell monitor.
Note: all Dell monitors work OK with different DP sources or PC and unfortunately we can find only one sample of each Dell monitor in the lab.
Note: also, when it work or does not work, the result is consistent on multiple attempts
Since we set CAD_SNK pin = 0 (DP sink), I assume the link training is monitored by the DP130 and it sets automatically output swing, pre-emphasis gain and equalization gain according to training info. What else can we do better if we choose to do manually?
If it is signal integrity, what can we improve on re-driver side?
Would you please share your schematic?
Are you able to see the display with a shorter DP cable?
On the non-working DP monitor, do you see HPD_SNK go high?
Do you have a AUX monitor that can capture the AUX traffic?
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In reply to David (ASIC) Liu:
The circuit works but the output signal looks worse that the input signal. See attached doc for more details.
In reply to lam huynh:
1. Since both waveform have a DC offset, it looks like you are measuring at the front of the AC coupling capacitors. You should measure the waveform after the AC coupling capacitors to remove the DC common mode voltage.
2. You should measure the output at the end of the trace. Measuring at the AC coupling capacitors will include reflection into the waveform.
3. You can disable link training, and tweak the DP130 RX equalizer and TX SWING and Pre-emphasis level to see if you are getting a better eye waveform.
When we use DP130 on receiver path, notice that when we program the DP130 with link training OFF and then go programming the DPCD registers, we read back OK but then when we initialize our FPGA DP receiver, something going on between the DP130 and the FPGA such all DPCD content set back to default. I am pretty sure that the FPGA cannot reset the DP130 as the only connection between them are the 4 TMDS pairs, the AUX link and HPD and that is all. On-board MCU controls the DP130 reset but the FW engineer told me he did not reset anything.
Question: can the DP130 reset it-self when info on AQUX link becomes overwhelming despite link training is OFF?Thanks
No, DP130 will not reset itself. Can you probe the DP130 power and RESET signal and make sure they not toggling when FPGA receiver is initializd? Or if you initialize the FPGA receiver and then change the DPCD registers, do you see the DPCD registers change again when you read it?
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