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DP83867IR: DP83867IRPR,XGMII_ERR_INT ,the receiver and transmitter can’t work great

Prodigy 80 points

Replies: 10

Views: 227

Part Number: DP83867IR

My design is using a DP83867 connected to a Xilinx Zynq running Linux.  When connect 1000Mb-T,The receiver works great,but the transmitter can‘t work in high speed, only can reach  kb speed . When connect 100Mb-TX,the receiver and transmitter can’t work great ,only can reach kb speed .

I can ping other addresses correctly.

I've noticed in the ISR register 0x0013 that bit 2 XGMII_ERR_INT is set 1 witch is diffrent from demo.  

someone say the problem maybe the 25Mhz clock  or 33.33Mhz clock,I confirm the two points,they are ok;

besides,how  can i change the register value trough the net on linux systerm?

Does anyone know what cause the problem?thankyou

  • Hi,

    Can you please specify exact speed you are getting ? When say 1Gb/s, it's the Physical layer speed, and Application ?

    Also, you may want to check

    a) PHY Register 1  thru MDC/MDIO interface to know the link status and speed of the PHY

    b) RX_CLK shall be 125 MHz for 1000M link and 25 MHz for 100M link.

    Regards,

    Geet

  • In reply to Geet Modi:

    HI:

    Can you please specify exact speed you are getting ? When say 1Gb/s, it's the Physical layer speed, and Application ?

    it means to connect the 1Gb/s or 100Mb/s external net;

    PHY Register 1  thru MDC/MDIO interface to know the link status and speed of the PHY

    1Gb/s:

        Register 0X0000: 0X1140

        Register 0X0001:0X796D

        Register 0X0011:0XAF02

    100Mb/s:

        Register 0X0000: 0X1140

        Register 0X0001:0X796D

        Register 0X0011:0X6F02

    RX_CLK shall be 125 MHz for 1000M link and 25 MHz for 100M link.

    1Gb/s:

        RX_CLK: 125MHz

        GTX_CLK:125MHz

        CLK_OUT: 25MHz

    100Mb/s:

        RX_CLK: 25MHz

        GTX_CLK:25MHz

        CLK_OUT: 25MHz

  • In reply to user4233086:

    Hi,

     The clock looks at correct frequency as well as the status register. From above, the PHY is linking in the correct speed.

    Next you may want to look if RGMII interface is configured correctly. You can perform PCS loopback and check if you are receiving all packets transmitted from MAC back on Rx path.

    Regards,

    Geet

  • In reply to Geet Modi:

    HI:

           what do you mean RGMII interface configuration?RGMII Timing frequence?

          The strap configure register 0X6E :0XA8

                                                              0X6F:0X3000

          how can i do PCS loopback?

          how can i write register trough MDIO iterface on linux platform?

  • In reply to user4233086:

    Hi,

    Yes, you can write the MDIO interface thru linux driver. Refer to register 0 for how to perform MII loopback.

    regards,

    Geet

  • In reply to Geet Modi:

    ok,thank you very much;

    So,I must perform MII and PCS loopback first.

     the ISR register 0x0013  bit 2 XGMII_ERR_INT is  1 ,what can result in this?this may cause these problems?

  • In reply to user4233086:

    It may point to issue in Clock ppm difference between MAC and PHY. You may want to check the clock quality of the TX_CLK.

    Regards,

    Geet

  • In reply to Geet Modi:

    Hi,

     

    I am closing this thread. In case you need further assistance, please open new thread and provide reference to this thread.

     

    Regards,

    Geet

  • In reply to Geet Modi:

    HI,

    now,i  still have 2 problem:

    1.the host can transmitte  data packets   correctly. afer pass the PHY,the short packets transmission (200 bytes)  is no problem,but when transmitting long packets(1400bytes),issues occur.  for example ,1400bytes,the front packet bytes is correct  ,but  the last packet bytes  loss all .

    by the way,normal  64 bytes ping,it's no problem. when ping 1400 bytes,data loss very Seriously.

    2.In normal operation mode ,soft-reset can work correctly.  When MII loopback , after soft-reset ,the PHY can not link normally. additionally,the same cords and the same configuration can work normally on Xilinx DEMO  board.

    please help me analyse the cause,thanks very much!

  • In reply to user4233086:

    We have another thread running. Closing this thread.

    Regards,

    Geet