This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

PCA9306: EN input requirements when used in the "Switch Configuration"

Part Number: PCA9306

Will the PCA9306 function properly as a simple I2C switch given the following conditions?

1. Vref1 = Vref2

2. EN pin is tied to Vref2 (not driven by a GPIO as shown in the datasheet)

Represented graphically, will the device function properly as a simple I2C switch if configured with the EN pin connected as shown by the green line below?

I am concerned by the many instances in the datasheet which seem to indicate that Ven must be Vref1 + Vth, while section 8.1.5 states that the GPIO driving EN must not exceed Vref2 + Vth.  These two pieces of information seem to contradict one another.

  • Hi Paul,

    If EN is tied to VREF2, how would you plan to switch the device off?  Are you planning to switch VREF2 on and off?

    The device does function with VREF1 = VREF2, but there are some minor functional differences to consider.  When VREF2 is higher it allows the device to bias the internal switches gates to a voltage above VREF1 such that when the voltage on either side pulls lower than VREF1 the switch begins conducting immediately to transfer the "low" level from side to side.  With VREF1 = VREF2 you don't have this extra headroom for internal biasing so instead the switches will start to conduct once the voltage on either side drops below VREF1 - Vth (~600 mV).  In most applications this is fine, although it will affect things like propagation delays through the switch.

    Regards,
    Max

  • Hi Max,

    Thanks for your reply.

    Yes, we would switch Vref2 off (while Vref1 remains powered) to disable the device.

    With that said, your answer does not explicitly address my initial questions.  Will the device be enabled for use as a simple switch if:

    1. Vref1 = Vref2

    2. EN pin is tied to Vref2 (not driven by a GPIO as shown in the datasheet)

    Again, I am concerned by the many instances in the datasheet which seem to indicate that Ven must be Vref1 + Vth, while section 8.1.5 states that the GPIO driving EN must not exceed Vref2 + Vth.  These two pieces of information seem to contradict one another.

    Thanks for the info regarding propagation delay.  We will take that into account once we understand the implications of our questions above.

    Thanks again,

    Paul W.

  • Paul,

    Yes, this connection can be used to operate the device as a switch.  When VREF2 is off, the device will be high-Z and so SDA1/SCL1 will not be affected by the low levels on SDA/SCL2.  When VREF2 is on, the device will conduct when the voltage on either side decreases below VREF - 600 mV in order to pass logic "low" levels between sides 1 and 2.

    Regarding the statement about EN not exceeding VREF2 + Vth, note that this relates to a configuration where VREF2 = VREF1.  So, in this case those terms (VREF1, VREF2) should be interchangeable.

    Max

  • Great, thanks very much Max.