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DS90UB954-Q1: Question on RAW Mode / 913 to 954 connection

Mitchell
Expert 4915 points
Part Number: DS90UB954-Q1

Hi Team,

My customer has a camera module which uses a '913 Serializer taking parallel pixel data. On the other end, there's an ECU which has a 954 that produces CSI MIPI to and FPGA w/ MIPI input. We have a couple questions on the RAW modes- our understanding is we need to set 954 into RAW mode when used with 913.

Question(s):

1) Please confirm transferring YUV422 8b parallel data through 913 SER across FPDLink and Deserialized by 954 DES is feasible?
2) If so, what is the CSI Data Type (DT_ that we would expect to see at the output of the 954 Deserializer? DT = h E (YUV422) or DT =h A (RAW8)
3) What is the line rate calculation if 8 bits of data + 2 sync bits. Assume fPCLK ~ 60MHz. If the equation can be provided, that would be best. 4 lane MIPI PHY is the interface from the deserializer to our FPGA.

Thanks,
Mitchell

  • 0
    TI__Mastermind 30515 points

    HI Mitchell,

    sorry the RAW description in UB913a/ub954 combo make you confuse. As you know, our UB913a only has either 10bits data input or 12bits data input due to pin limitation, this is called as RAW10 or RAW12 but actually this is NOT specified as "data type" for CSI2 format.

    If you pair UB954 with UB913a or UB933, as d/s mentioned, you can set the RAW10 or RAW12 mode. If the input data is YUV422-8-8, you need select RAW10 mode (mode_sel pin of UB954 should be set as RAW10, reg. 0x6d[1:0] must be 2b'11), then you can set the other 2registers to make the link work in the correct mode:

    a. reg. 70[5:0] must be set as YUV422-8-8 data type 0x1E (default is raw10 0x2b)

    b.1. reg. 0x7c[7:6] is set as either upper 8bits or lower 8bits dependent on your UB913a's pin usage (upper 8bits -D2~D9 or lower 8bits D0~D7)

    b.2. reg.. 0x7c[1:0] sync. polarity from the camera

    For your issues:

    1. yes, it is the typical application since most ISP output is YUV422

    2. DT - reg.0x70 is set as 0x1E (defined by CSI2 spec.)

    3. the UB954 CSI2 output is limited as 800M, 400M or 1.6Gbps, you can use below calculation:

    a. video data bandwidth: 60MHz x16bits =960Mbps (but our UB913A can support this as "PCLK" in UB913a only is 100MHz for RAW10 mode, and every pixel needs 2 "PCLK", if you think video PCLK is 60MHz, it means UB913A's "PCLK" is 120MHz)

    b. pls add ~25% blanking as sync. / blanking signals, to totally the CSI2 bandwidth can be <1.25Gbos in your case, you can set 2lanes and 800Mbps/lane as UB954's CSI2 output.

    best regards,

    Steven

  • 0 in reply to Steven(Shenzhen) Shi
    Prodigy 60 points

    Thank you Steven for your response. Regarding your 3a comment:

    "video data bandwidth: 60MHz x16bits =960Mbps (but our UB913A can support this as "PCLK" in UB913a only is 100MHz for RAW10 mode, and every pixel needs 2 "PCLK", if you think video PCLK is 60MHz, it means UB913A's "PCLK" is 120MHz)"

    This implies that if I have 2MP@30 FPS sensor with YUV422, my PCLK is 2MPx30FPS = 60MHz, I would not be able to support it? At most, I could support 2MP @25FPS (50MHz PCLK -> UB913A "PCLK" is 100MHz)?

    Regarding 3b, I can still choose to use 4 lane MIPI output @ 400Mbps/lane correct?

  • 0 in reply to Jeffrey C
    TI__Mastermind 30515 points

    hello,

    1. exactly. For 2M@30fps, you need select ub935 or ub953 solution with MIPI I/f

    2. yes. you also can select 2lanes & 800Mbps/lane.

    regards,

    Steven

  • 0 in reply to Steven(Shenzhen) Shi
    Prodigy 60 points

    Thank you again Steven. One more question regarding:

    "and every pixel needs 2 "PCLK""

    Why does every pixel need 2 "PCLK"s? Is that described in the the DS90UB954 data sheet somewhere?

    Jeff

  • 0 in reply to Jeffrey C
    TI__Mastermind 30515 points

    Here, the "PCLK" is for UB913's PCLK input pin signal. As mentioned, 1PCLK in UB913 side only can clock 8bits, if 1pixel has 16bits, you need 2PCLK cycles to clock 1pixel signal in the parallel side of UB913a.

    regards,

    Steven