• Resolved

DP83867IS: Link between 2x DP83867IS with only 2 wire pairs

Prodigy 50 points

Replies: 6

Views: 108

Part Number: DP83867IS

Hello everyone,

we're developing a board with 4x DP83867IS PHYs. Of these
- 3 are connected to a backplane connector through a transformer with 4 wire pairs for 1Gbit/s
- 1 is connected to a backplane connector through a transformer with only 2 wire pairs for 100Mbit/s only.

Several boards will be connected in one system and we get the following connection scenarios:

- 4 wire pairs to 4 wire pairs -> works fine
- 4 wire pairs to 2 wire pairs -> doesn't work
- 2 wire pairs to 2 wire pairs -> doesn't work (as expected, basically same as previous scenario)

We've observed that no link is established, or a supposedly 1Gbit/s link is established, when only 2 wire pairs are used.
The way I understand the datasheet using only 2 wire pairs should pose no problem and a link with 100Mbit/s should be established. Unfortunately, reality seems to disagree.

Forcing the link speed in software resolves the issue, but our customer requires a stable link-up shortly after power-up without any software involved, so this is not an option for us.

The unused MDI signals are connected to ground via 1kOhm resistors.

Can you give any advice on why the auto-negotiation doesn't work reliably or how we can improve it?

Thank you!

Regards
Ferdinand

  • Hello Ferdinand,

    The auto-negotiation happens on the MDI side of the PHY. In other words each of the 4 individual PHYs will auto-negotiate with their corresponding processors / LAN partners on the other side of the RJ-45 connection and not with each other (they are communicating via on-board xMII).

    The speed of each individual PHY is set by the external connection through which information is coming into the board. If the different PHYs are set to different speeds through auto-negotiation there will be issues with link-up.

    Thanks,

    Vibhu

  • In reply to Vibhu Vanjari:

    Hello Vibhu,

    it seems there was a misunderstanding regarding our setup, so I made an illustration for clarification:

    The ethernet PHYs should establish a link to another PHY without the CPU involved, and even if the CPU is in reset. For cases like board 1 ETH2 to board 2 ETH1 with 4 wire pairs this works fine. But when only two wire pairs are available no link is established.

    My expectation is that as soon as the system is powered up, while the CPU is still in reset
    - board 1 ETH4 and board 2 ETH3 establish a 100Mbit/s link
    - board 1 ETH3 and board 2 ETH2 establish a 100Mbit/s link
    - board 1 ETH2 and board 2 ETH1 establish a 1Gbit/s link

    Why is it that only the 1Gbit/s link is established?

    Regards
    Ferdinand

  • In reply to Ferdinand Grossmann:

    Hello Ferdinand,

    To achieve 1G link, regardless of type of MII interface being used all 4 pairs of MDI must be used. With 2 pairs you can establish 100M/10M links.

    Your expectation aligns with my thoughts on this.

    However, auto-negotiation is defined to work on channels A & B of an Ethernet PHY. This is why you see that they link up at 1G, only to immediately have the link drop.

    Your options are to either disable the 1G advertisement on the CFG1 register, force speed to 100M or to enable speed optimization on CFG2 register (the latter is more of a debug feature). All three options will require register programming.

    Thanks,

    Vibhu

  • In reply to Vibhu Vanjari:

    Hallo Vibhu,

    I have printed out the register map from the datasheet for the PHY and there it says the default for SPEED_OPT_EN is 1.
    However, when I look at the newer datasheet version (I printed the one from October 2015) it says the default is 0. There is no notice on this in the revision history, though.

    Could you please confirm what the default value for this bit is and if it has been changed in the datasheet update the revision history to include the info?

    Thanks!

    Regards
    Ferdinand

  • In reply to Ferdinand Grossmann:

    Hello Ferdinand,

    This is recorded in the revision history as "Changed default of bit 9 from '1' to '0' in Table 28".

    The default value of SPEED_OPT_EN is 0.

    Please let me know if the suggestions I've given above resolved your issue.

    Thanks,

    Vibhu 

  • In reply to Vibhu Vanjari:

    Hello Vibhu,

    sorry, my mistake - I didn't catch the entry in the revision history.

    Since I looked at the old version of the datasheet I always assumed that the speed optimization was enabled by default. But it isn't, and what I see is in accordance with the datasheet.
    That was what caused my confusion.

    Now it's become clear and the I see the issue as resolved.

    Thank you!

    Regards
    Ferdinand