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Part Number: DP83867IR
We have a board using the DP83867IRRGZT part. We have a problem with CRC errors on the link. It seems that the analog side is the problem. With reverse loopback enabled, we get about 5% packet loss, and the computer interface says they are due to CRC errors. We are using the TE integrated magnetics 6-2301994-1, which from what I can see meets all the requirements for the magnetics. We designed the board with 100 ohm differential impedance, and we use TPD4E05U06DQAR TVS components on the data lines on the PHY side of the magnetics.
The link comes up and works normally apart from the packet loss. I have gone through the troubleshooting guide, and I don't see anything in there that is a problem.
I would appreciate any ideas for getting this fixed.
When you mention that the magnetics chosen meets all the requirements, what specifications have you compared?
What is your clocking solution, are you using a crystal or an oscillator? What is the ppm error?
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In reply to Vibhu Vanjari:
Hi. I got the specs from AN-1469, the PHYTER design app note. I didn't see any specs in the DP83867 data sheet. Here's the specs from the TE data sheet.
The clock is an oscillator, driven by the 1.8V rail. The part is the Abracon AMPMGFB-25.0000T, +- 25 ppm stability.
Today I went through the IEEE Ethernet compliance testing for the 1000 Mb case. I don't have a compliance tester, but I captured the waveforms for the various tests, and at least the waveforms look right. I did the mode1 test by hand, and it seems like all 4 channels are the same, and I think they all pass the tests to the limit of my measurement ability. All the channels look the same, with a bit of overshoot on the second half of the plot.
In reply to John Ford75:
Here's a picture of the layout of the PHY to MDI interface.
Were you able to achieve a solution for this?
If so can you drop me an email to firstname.lastname@example.org
I have some more information from testing today.
We see zero errors running the loopback test from the MAC to the digital loopback point (Reg 0x0016 set to 0004). If we extend our test to the analog loopback point setting register 0x0016 to 0008, we see a few errors creep in, about 2 or 3 every 65k packets. Is this normal? If not, what can cause it?
Also, we tested the 100 Mb and 10 Mb interfaces, and usning the reverse loopback we can send packets error-free from the host to the board and back with the 10 Mb interface. We get a few errors on the 100 Mb interface, and many more errors on the gigabit interface.
We are using an Intel EN5319QI Power SOC power supply for the chip's power supplies. Is it OK to use these; or do we need linear supplies? I notice that the eval board uses an LDO for the 2.5 and the 1.0 volt power supplies.
Any ideas for us?
Sorry for the delayed response. If this issue is still open, would you be able to do the same tests with the EVM and see if you see the same issues at 100M and gigabit?
As long as the power supplies meet the requirements in the datasheet there shouldn't be an issue. Is there a way to use an external supply on the board, to see if that makes a difference?
Some info of my debugging in progress:
1. In Analog Loopback you should have the 100E Terminated across 1Gbps Pairs to work successfully (i had to do this)
2. Am running with the same issue as yours(Digital loopback works fine for me, Reverse and analog loopback gives trouble) - I have done this
3.Also i checked if MAC received packets in reveres loopback failed condition and they didn't (So the Phy is not sending it through)-I have done this
4. I would recommend to check the CLK_OUT pin to have it to decoded the receive clock from MDI when packets drop across ->Am yet to do this
5. Are using PRBS when doing Loopback or sending packets from MAC?(reason: we can check if PRBS is in sync if PRBS is used)->Am yet to do this
6. Can you check in LEDCR1 if receive error or transmit error bit is set or if you can decode from RGMI side from RX_CTL and RX_CLK ->Am yet to do this
7. Am not if it will impact check 220.127.116.11 Clock In (XI) Recommendation of datasheet-> I have not followed this
In reply to Balaji Padmanaban:
Thanks for the input. I will try some of these things.
Some info of my debugging in progress
Thanks for the idea. I will try this. I tried it with the cable unplugged, plugged in to a computer (very bad results), but I did not try it with a terminated cable.
This is OK
I have nit tried this yet. Will do so
Also a good idea. I will try it.
I have checked this. My clock is well within spec.
I will try the tests on the EVM.
I am going to try to power up the board with linear supplies and see if that helps. The noise on the 1, 1.8, and 2.5 supplies are withing spec as far as the data sheet goes.
Is our board layout reasonable as I showed it in a recent post? We may try to respin the board with some different layouts to try to get a reliable link if you think we should look into that. I don't seem many if any examples of gigabit ethernet with a magjack. The TI EVM uses a discrete magnectics and connector.
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