Hi Team,
When measuring the timing of the screen, we found some problems in I83's LVDS clock and data signals. When there is no signal output in I83, there is a bias voltage of 1.2V 3.12S. Can this bias voltage be set to low level before LVDS output?
Please see the figure below for the situation. Because this bias voltage will be reversed to 3V3 of the screen, forming a voltage of about 1V, which may affect the screen's failure.
