Other Parts Discussed in Thread: LMH1218
Hello.
We've faced issue with LMH1219 which looks like over-equalization in one of our designs.
Our device is 12G-SDI I/O board (based on Xilinx's FPGA) with two inputs (LMH1219) and two outputs (LMH1218). Outputs seems working good in 12G mode - video can be received by 3rd-party 12G-SDI devices, inputs works adequate only in <=6G-SDI mode. First of all, circuit:
We have some own software, that can read/write LMH12xx registers and read eye diagram.
Case 1: 3rd party 12G-SDI converter as source, short (0.5m) belden 4855R cable. Here is eye diagram:
in this case LMH1219 de-asserts lock_n (lost lock) several times per second, also we can see a lot of bit erros in SDI stream. Interesting thing, that if we disable cable equalizing (reg 0x27 = 0x0c) everything starts working perfectly, and eye looks like:
Case 2: Board output (LMH1218) as source, short (0.5m) belden 4855R cable. Everything getting worse:
LMH1219 never asserts lock_n (always unlocked), disabling equalizer leads to case 1 (with eq enabled).
What could be the reason for this behavior?
Also, I was thinking that our PCB design may be imperfect (it came from old 3G-SDI design):
(latter is nearest GND layer, all other layers has similar cutouts)
Can such pcb design cause this issue?