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DP83867IR: DP83867

Part Number: DP83867IR
Other Parts Discussed in Thread: DP83867E

Using a TI 83867 PHY with Zynq, having issues with PING command.  On doing PHY reg reads, all reg values are reported as 0. It is a 100M port. 

The RGMII clock skew is done in PHY (Mode 1 strap option). I have checked power supply, clock, bias resistor values.

The PING command sometimes work but majority of the time reports: Request Timed out.Reg Dump Dec 6 2012 Jan 01 01.docx

  • Hello Dalip,

    Please help me understand the document you sent me. It looks like there are some registers that you are able to read while, there are some that you cannot.

    It looks like you have two PHYs one with address 0xf and one with address 0x15.

    Please take a look at section "8.4.2.1 Extended Address Space Access". To access the extended registers please follow the steps listed in this section. Particularly "8.4.2.1.7 Example of Read Operation Using Indirect Register Access" and "8.4.2.1.8 Example of Write Operation Using Indirect Register Access" may be of interest.

    Thanks,

    Vibhu

  • Hello Vibhu,

    Thanks for getting back to me quickly.

    I do have two PHYs (0xf or 0x15) and 0x0.  The both PHYs are set to 100M. Auto-negotiating is turned off for both. PHY 0xf is not configured through Zynq.

    The other  PHY 0x0 does get configured through Zynq's MII-RGMII converter.

    This is the PHY 0x0 that is not working properly. It works very intermittently or does not work at all. I have checked power supply, the biasing resistor etc.

    So when PHY 0x0 does work, I am enclosing the register read-outs. When it does not work, you don't get any register values read. They are all reported as 0x000.

    I am attaching the PHY 0x0 register values when it does work.  And also, the PING replies (it shows sometimes PING works correctly and majority of the time it fails).

    The RGMII Clock skew for PHY 0x0 is done via strapping (Mode 1). I have checked that Zynq is not setting the Clock Skew.

    thanks.

    Dalip.PHY ADDR 0 Reg Values when It is working .docx

  • Hello Dalip,

    Can you confirm that you are following the procedure described in the datasheet for accessing the extended register set?

    Thanks,

    Vibhu

  •  

     

    "Please take a look at section "8.4.2.1 Extended Address Space Access". To access the extended registers please follow the steps listed in this section. Particularly "8.4.2.1.7 Example of Read Operation Using Indirect Register Access" and "8.4.2.1.8 Example of Write Operation Using Indirect Register Access" may be of interest."

     

    What document are you referring to above? The DP83867 datasheet? or some other doc.  As I cannot find it in the datasheet.

    And like I said reading the registers, per se, is not the issue. It is the intermittent functionality of the PHY 0x0.

    Thanks.

  • It is section 9.4.2.1... I did find it. The section numbering is different in the datasheet that I have.  The extended register set is properly accessed. My SW team took care of that.  I have a script that is spitting the Registers via serial port.

    My issue is intermittent functioning of the PHY 0x0 which is configured through Zynq (RGMII-interface).

    As you can see in the PING capture that i sent.

  • Hello Dalip,

    Sorry for the confusion with the section numbering. I was referring to the DP83867E datasheet.

    Thanks for confirming. I am still a bit confused on how you are configuring the device. How are you configuring the PHY through Zynq if this is an RGMII interface. You need to configure the PHY via SMI (MDIO + MDC) interface. Does the Zynq also provide the SMI interface to configure the registers?

    Thanks,

    Vibhu

  • Please check the word doc for my configuration.

    PING not working.docx

  • Hello Vibhu,

    So this is my PING screens....the link works mysteriously and then goes down.

    And this PHY ,if at all works and that too very intermittently, if I use large packet (max=65500) for PING. I don't understand what makes it work albeit for minuscule amount of time when 65500 is used.

    PING Behavior .docx 

  • Hello Dalip,

    See my question above:

    How are you configuring the PHY through Zynq if this is an RGMII interface. You need to configure the PHY via SMI (MDIO + MDC) interface. Does the Zynq also provide the SMI interface to configure the registers?

    Here are some troubleshooting steps:

    1. Probe RX_CLK, if there isn't a clock here then there was an issue with powering up the PHY
    2. When you say that the PHY is intermittently working does that mean, when it does work you are able to read registers 0x2 and 0x3 and compare with datasheet and values match?

    Thanks,

    Vibhu

  • It is the same thread. 

    I will check the RX_CLK.  

    The registers are able to be read but when the PHY is not functional (no PINGs passing), all the register values are read as 0x00.

    I did conduct one specific test: I ftp'd two large files 500 M and 1G across the ethernet port/PHY in question. I then retreived them back. Did a checksum on the files for corruption and they checked good.

    The issue : PING command fails on this particular PHY.

    I will get back to you how PHY is configured.

  • Hello Dalip,

    Thank you, please keep me posted on the progress. 

  • Hello Dalip,

    I am closing this thread, please open a new thread when you have the information on register configuration process and RX_CLK probe data.

    Thanks,

    Vibhu