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DP83TC811S-Q1: TRD_P/M Signal Input under Power Off

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Replies: 1

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Part Number: DP83TC811S-Q1

Hi Team,

My customer is evaluating DP83TC811S-Q1 and has some questions as follows,

Q1. Under power off, VDDA=VDDIO=0V of the DP83TC811S-Q1, if 100BASE-T1 signals are inputted into TRD_P/M of the DP83TC811S-Q1, are there any issues on the DP83TC811S-Q1?

Q2. Datasheet of the DP83TC811S-Q1, Timing Requirement on page 14, has ramp rate of VDDA and VDDIO at Power-Up Timing.
       VDDA and VDDIO ramp rate: Min=0.165 V/ms, Max=33 V/ms
       If the ramp rate was faster or slower than Min-to-Max range, what would happen on the DP83TC811S-Q1?
       Especially, if the ramp rate was faster than Min spec, what would happen on the DP83TC811S-Q1?

Q3. If the DP83TC811S-Q1 is Slave, is it possible to do the Compliance Test?

Thank you.

Best Regards,

Koshi Ninomiya

  • Hello Koshi,

    Q1: If the DP83TC811 is not being powered, then the PHY will not be on, therefore no signals could go through. 

    Q2: The timing requirements listed on page 14 are the specs for the part. You should expect to see the timing between these values.

    Q3: Correct, you are still able to do compliance testing.