CCS/TCAN4550-Q1: How to set up CAN FD Bit rate manually

Hi Alex,

Thank you for your interest in the TCAN4550. It is hard to say with certainty whether your settings are correct because it all depends on what your Clock Input frequency is that the TCAN4550’s CAN-FD Controller will use as a basis for setting the bit rate. Common clock frequencies used in CAN-FD applications are 20MHz, and 40MHz and will determine the amount of “Time Quanta” available to you. The timing settings are simply an allocation of the available time quanta for your desired bit period. You didn’t specify this in your post so I will have to make some assumptions.

If you have not already read the TCAN4x5x Software User’s Guide, it is a good reference and section 4.1 outlines the Bit Timing setup and gives an example. We have not published a separate App Note about configuring the Bit Time settings, but hopefully the information in the Software User’s Guide will be sufficient. This post also addresses the bit timing allocations that you might want to reference.  I will also go into greater detail to help document this topic for others who may read this thread.

From your desired settings, it appears you are using a 40MHz Input clock. I am also assuming that you are subtracting 1 from your settings to account for the fact that the TCAN4550 will interpret those settings as 1 greater than the set number and thereby assuring no value can be equal to 0.

For your desired Header settings:

Header: 500Kbps, SP 80%, BRP 1, TQ 40, Prop + PhSeg1 31, PhSeg2 8, SJW 8.

/* Configure the CAN bus speeds */
TCANNomTimingRaw.NominalBitRatePrescaler = 2 - 1;
TCANNomTimingRaw.NominalTimeSeg1andProp = 31 - 1;
TCANNomTimingRaw.NominalTimeSeg2 = 8 - 1;
TCANNomTimingRaw.NominalSyncJumpWidth = 8 - 1;

I notice there is a mismatch between your BRP (Bit Rate Prescaler). Your customer specification lists “BRP 1” and you have set your NominalBitRatePrescaler to 2-1 ( => 1, but interpreted as 2 by the TCAN4550). With a 40Mhz clock and a bit rate of 500Kbps, this will give you 80 clock cycles. A BRP of 1 will give you 80 Tq (Time Quanta) per bit, and a BRP of 2 will divide that by 2 and give you 40 Tq per bit. However your specification also states “TQ 40” so your setting of BRP to 2 is correct.

The Sample point will be located between Phase 1 and Phase 2. We can simply count how many Tq are before and after this point and calculate the percentage. There is always 1 Tq used for Sync. Therefore we can add the Sync to the Prop + Seg1 => 1+31 = 32 Tq. The total Tq is 40 based on the System clock and BRP. Therefore we can verify the setting of Seg 2 to 8 Tq is correct (40-32 = 8). And the sample point is verified by 32/40 = 0.8 or 80%.

Therefore your Nominal Bit Time settings look correct for a 500Kbps bit time using a 40Mhz clock frequency.

Let’s look at your Data bit timing settings in the same way once again assuming a 40Mhz clock frequency.

Data: 2.0Mbps, SP 80%, SSP 80%, BRP 1, TQ 10, Prop +PhSeq1 7, PhSeg2 2, SJW 2, TDC 8TQ

TCANDataTimingRaw.DataBitRatePrescaler = 2 - 1;
TCANDataTimingRaw.DataTimeSeg1andProp = 7 - 1;
TCANDataTimingRaw.DataTimeSeg2 = 2 - 1;
TCANDataTimingRaw.DataSyncJumpWidth = 2 - 1;
TCANDataTimingRaw.TDCOffset = 8 - 1;
TCANDataTimingRaw.TDCFilter = 0;

Once again there is a mismatch between your BRP settings. But with 20 clock cycles available in a 2Mbps bit period, and a DataBitRatePrescaler = 2-1 (=> 1, but interpreted as 2 by the TCAN4550) will give you 10 Tq per bit, just as the “TQ 10” specification states. So this looks correct.

Once again the Sample point will be located between Phase 1 and Phase 2. We can simply count how many Tq are before and after this point and calculate the percentage. There is always 1 Tq used for Sync. Therefore we can add the Sync to the Prop + Seg1 => 1+7 = 8 Tq. The total Tq is 10 based on the System clock and BRP. Therefore we can verify the setting of Seg 2 to 8 Tq is correct (10-8 = 2). And the sample point is verified by 8/10 = 0.8 or 80%.

Therefore your Nominal Bit Time settings look correct for a 2Mbps bit time using a 40Mhz clock frequency.

You will also need to set the TDCO (Transmitter Delay Compensation Offset) register to match the "interpreted" value of DTSEG1 value.  The TDCO does not interpret the value as 1 greater than the set value, so TDCO = DTSEG1 + 1.  This would mean you would want to set the TDCO to 7 =0x07.

The TCAN4550 contains the Bosch M_CAN 3.2.1.1 controller IP and I would recommend you also download and reference the M_CAN User’s Manual located on Bosch’s website. I will note that the current version is 3.3.0 and the TCAN4550 uses 3.2.1.1 and therefore there may be a few differences between the two. You can most likely find the 3.2.1.1 User’s Guide by searching for it online. The TDC (Transmitter Delay Compensation) register descriptions can be found in the M_CAN User’s Manual. It wasn’t practical to duplicate all of the M_CAN register settings in the TCAN4550 datasheet, I would recommend you treat the M_CAN User’s Manual as a supplemental document as you proceed with your firmware development.

Regards,

Jonathan

Hello, Jonathan.

Fist of all, Thank you for your good response again.

I’m really sorry about that not only there isn’t certain information for you but also I gave you misinformation.

While I implemented some features, I was complicated so that I made mistyping. I want to correct my previous question like below.

1. My main clock is 40MHz. And also your guessing is correct.
2. My desired setting BRP is 2, thereby TCAN4550 can use 20Mhz for making bit rate.

First time, I tried to set up bit rate based on Code_sllc469a library. But I couldn’t help using raw configuration function instead of simple configuration function in C-Code. Because, I wasn’t able to set up bit rate setting value for my customer.

According to your answer, I corrected my desired value. Could you check this again?

Desired setting value (Main Clock 40Mhz)

Header: 500Kbps, SP 80%, BRP 2, TQ 40, Prop + PhSeg1 31, PhSeg2 8, SJW 8.

Data: 2.0Mbps, SP 80%, SSP 80%, BRP 2, TQ 10, Prop +PhSeq1 7, PhSeg2 2, SJW 2, TDC 8TQ

Register setting value

/* Configure the CAN bus speeds for 500Kbps*/
TCANNomTimingRaw.NominalBitRatePrescaler = 2 - 1;
TCANNomTimingRaw.NominalTimeSeg1andProp = 31 - 1;
TCANNomTimingRaw.NominalTimeSeg2 = 8 - 1;
TCANNomTimingRaw.NominalSyncJumpWidth = 8 - 1;

/* Configure the CAN bus speeds for 2.0Mbps*/

TCANDataTimingRaw.DataBitRatePrescaler = 2 - 1;
TCANDataTimingRaw.DataTimeSeg1andProp = 7 - 1;
TCANDataTimingRaw.DataTimeSeg2 = 2 - 1;
TCANDataTimingRaw.DataSyncJumpWidth = 2 - 1;
TCANDataTimingRaw.TDCOffset = 8 - 1; (Delete '-1')
TCANDataTimingRaw.TDCFilter = 0;

Lastly, I’m still curious about TDC Filter, because I don’t have specific knowledge of M-CAN made by BOSCH. I’ve been able to understand about TDCOffset by referring to Bosch M_CAN 3.2.1.1. However in my customer requirement, There is no mention related to TDCFilter, So I set up TDCFilter as ‘0’. I’m still worried about side effect by TDCFilter. Could you let me know normal setting value for TDCFilter if TDCOffset is “x”.

Thank you.

Best regards.

Hi Alex,

Transceiver Delay Compensation is a feature of CAN FD and is needed with higher data rates in order to avoid sampling bit errors by allowing the controller to define a "Secondary Sample Point" where the transmitted bit is compared with the received bit in order to check for bit errors. 

Without a transceiver delay compensation, the bit rate in the Data-Phase of a CAN FD frame is limited by the fact that the Transmitter detects a Bit-Error if it cannot receive its own transmitted bit by the sample point of that bit.  Basically this is used in applications where the length of the CAN bit time in the Data-Phase is shorter than the limit required by the transceiver's internal delay time.

In Bit Time Requirements for CAN FD a document written by Florian Hartwich, Robert Bosch GmbH who developed CAN FD, he discusses this in greater detail.  I will give you a basic overview, but I won't try to improve upon the original source which I have linked to.

As I am sure you are aware, the CAN controller monitors the transmitted bits and compares them to the received bits.  This allows for arbitration between the nodes allowing the controller to know if there is a node transmitting with a higher priority message than itself and allows it to disable the transmitter until the bus is clear or when its message has the highest priority. 

But not only are the arbitration bits monitored, the data bits are monitored for accuracy, proper CRC values in the messages, etc. in order to be a check on the overall integrity of the system and to flag errors.  Therefore it is important that the controller sample the bit at a point in time where the bit is most likely to be valid to avoid false bit errors.  In Classical CAN, the Arbitration bit time and the Data bit time is the same.  However, in CAN FD, the Data bit time can be much faster and the bit time is much shorter making it harder to accurately sample the data bit. 

Remember there is a Transceiver Loop Delay on the bus formed by the physical medium, that makes up the bus.  This includes internal processor delays, PCB trace, Transceiver Internal Delay paths, and propagation delays on wiring harness itself, etc.  With fast bit times, the bit time can become shorter than this loop delay and therefore the Transmitter will never sample the same bit on both the Transmitter and Receiver at the exact same time and therefore cause every bit to be considered an "Error."

In order to compensate for this loop delay when checking for bit errors, a Secondary-Sample Point (SSP) is defined.  instead at the Sample-Point, the transmitted bits are checked at the SSP.  The result of that check is stored until the next Sample-Point is reached, where the protocol controller Finite State Machine (FSM) is evaluated. - (Florian Hartwitch, Robert Bosch GmbH)

We recommend the TDCOffset to be set to the same DTSEG1+Prop Time Quanta value as a general starting point which is usually good enough for most bus applications and have the controller not generate bit errors.  However, this may need to be adjusted depending on the final bus architecture and adjusted up or down to optimize the bus and prevent bit errors.

Currently your DTSEG1 + Prop setting will be interpret by the TCAN4550 as 7.

TCANDataTimingRaw.DataTimeSeg1andProp = 7 - 1; ==> 6 but interpreted as 7.

Therefore if you want the TDCOffset to be equal to this value, you will want to set the TDCOffset to 7 because the TCAN4550 does not interpret this as one greater than the set value because a setting of "0" offset is valid.

TCANDataTimingRaw.TDCOffset = 7

I would suggest you start with a matching value and then adjust from there in the final application based on performance.

Does this answer your question?

Regards,
Jonathan

Hello Jonathan.

Thank you for response.

I've been understand by referring to your advise for TDC and SSP.

And also I've set up my register based on specification. 

Thank you.~

Best regards.