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DS90UB934-Q1: HSYNC/VSYNC signals not present

Part Number: DS90UB934-Q1

I am using the 934 deserializer in conjunction with the 935 serializer connected to a CSI-2 (MIPI) image sensor. The SerDes is in DVP mode with an external FrameSync sourced from the deserializer end.

The video data out of the deserializer goes between active and blanking (all zeros) as expected, but HSYNC is always high and VSYNC is always low on their respective deserializer pins.

The issue is similar to this post: https://e2e.ti.com/support/interface/f/138/t/735724 

but I am using a CSI serializer so I can't verify SYNC presence in the same way.

I've attached the register settings of the SerDes devices, and noted the ones that have changed between resetting the chips and my initialization functions. Those register settings can be viewed in the table file below. Any other registers not mention can be assumed to be default.

0385.FS Reg Drop.pdf

Any advice would be greatly appreciated.

Regards,

Sam Shafer



  • Hi Sam,

    Is this the same issue from here: https://e2e.ti.com/support/interface/f/138/t/874818?tisearch=e2e-sitesearch&keymatch=%2520user%253A425383

    If so, we can close this thread and discuss the issues at the old thread.

    Best,

    Jiashow

  • Jaishow,

    I don't believe these issues are the same; the aforementioned issue is with remote GPIO signal integrity on the back channel. This is a complete lack of signal through the forward channel. Unless the Deserializer's ability to compute HSYNC/VSYNC signals depends on the sensors frame sync, the issues are indeed separate.

    I'm not sure what factors lead to the generation the H/VSYNC signals on the deserializer end. The datasheet for the 934 does not explain that functionality. Any further documentation or explanation would help me in tracking down the source of this error.

    Thanks,

    Sam

  • Update:

    I resolved the issue of the aforementioned post, but HSYNC and VSYNC signals are still no where to be found.

  • Here is a screen capture of the waveforms on the various 934 deserializer pins while the system is running.  Datain = ROUT. Notice how HSYNC stays high, VSYNC stays low. They have yet to ever change.

  • Hi Sam,

    Can you first check if valid CSI input is detected by the 935?

    You can check the packet header, payload, and CSI errors at 935 reg 0x5C, 0x61, 0x62, 0x63.

    Best,

    Jiashow

  • Here are the results to that test:

    SZR regs:

    0x5C is [0], 0x61 is [0] , 0x62 is [0] , 0x63 is [0]

    Update: I also ran a test on the following DSZ regs:

    0x55 [0],0x56 [0], 0xD0 [0], 0xD8 [0], 0xD9 [0], 0xDA [0], 0xDB [0]

  • It seems that the error is not caused my the MIPI interface between sensor and serializer. I suspect the source is th  deserializer, but cannot yet confirm.

    To reiterate, the register commands I've changed are: [Reg,Data]

    DSZ init
    [DSZ_RESET,0x7],[FPD3_PORT_SEL,0x11],[PORT_CONFIG,0x7B],[BCC_CONFIG,0xD8] ],[DSZ_CONFIG,0x3E],[FS_CTL,0x80],[GPIO0_PIN_CTL,0x01],[GPIO1_PIN_CTL,0x00],[BC_GPIO_CTL0,0x10],[BC_GPIO_CTL1,0x32],[BIST_CTL,0x00],[FPD3_PORT_SEL,0x01]

    SZR init
    [0x01,0x04],[0x02,0x03],[0x03,0x15] ,[0x04,0x05],[0x05,0x03],[0x0D,0x32],[0x0E,0x30],[0x10,0x0],[0x11,0x0] ,[0x17,0x0],[0x18,0x0],[0x20,0x00],[0x21,0x00],[0x32,0xC9],[0x49,0x28]

  • Update: I analyzed the MIPI signal coming out of the sensor. It appears to be correct in terms of line and frame data length, as well as short packet placement for indicating frame start and stop. I'll attach screen captioned scope captures.

    An issue I did notice is that the frame sync signal into the sensor is not synchronizing with the data coming out of the sensor. This indicated that the issue lies within the sensor rather than the SerDes components. I reached out to the sensor manufacturer for help and will keep this thread updated with any relevant information they provide.

    Attached are a few images of the MIPI signal:

    1) MIPI frame's first line signal

    2) MIPI end of frame signal

    3) Zoom on end of frame signal's data portion

    4) Frame start short packet (followed by blanking until first valid line)

    5) Zoomed in on frame start's packet data(Left part is fixed, left middle  is counting, right middle is fixed,  right part  may be checksumming)

  • Update: We fixed the synchonisation on the sensor end. Still no H/VSYNC on the Des end.

    Image below shows frame start signal on every clock rising edge

    Pink = Clock, Blue = Mipi Data

  • Hi Samuel,

    The sensor information should be available in 953 registers 0x5C, 0x61, 0x62, 0x63 if it's valid. Are they still reading 0x00 even after you fixed the synchronization? Are you getting consistent, error-free lock?

     Best,

    Jiashow

  • I reread those registers after the sensor started syncing to the frame sync. New values!

    935 Reg 0x5C: [0]

    Reg 0x61: [0x2B]

    Reg 0x62: [0xE8]

    Reg 0x63: [0x3]

    So the virtual ID from the CSI-2 packet header is: [0x1]

    The data ID is: [0xB]

    and the payload count is: [0x3E8]

  • Hi Samnuel,

    I see the 934 is set for RAW 10 bit mode: 10 bits of DATA + 2 SYNC bits for an input PCLK range of 50 MHz to 100 MHz in the 10-bit mode. Note: HS/VS restricted to no more than one transition per 10 PCLK cycles.

    Are the requirements for RAW10 mode met?

    Could you try to set to RAW12 HF mode and see if you are able to see the HS/VS signal? Can you also check section 6 Data Rate Calculations for the CLKIN input to make sure it's correct? http://www.ti.com/lit/an/snla270a/snla270a.pdf

    Best,

    Jiashow

  • Jaishow,

    What are the requirements for RAW10 mode? The pixel clock is EDIT: 80 MHz.

    I'll run the RAW12 mode and report back on those results..

    Thanks,

    Sam

  • Hi Sam,

    The pixel clock is too low. We require the camera to have at least 50MHz PCLK for RAW 10 and 37.5MHz for RAW12HF. Could you increase the frame rate on the camera to meet the requirement?

    Best,

    Jiashow

  • Hey sorry, type. I meant to say the pixel clock is 80 MHz.

    In 12 bit mode, there is still no movement on the HSYNC and VSYNC pins. Here is what the data looks like :

  • Hey Jaishow,

    This issue is preventing the development of my video processing system; the lack of synchronization signals is impeding proper video from appearing on my monitor. Further support would be much appreciated, as the issue seems to be with aspects of the SerDes devices not mentioned in the datasheet.

    I am considering implementing a rough hack to produce H/VSYNC signals by interpreting the video data and synchronizing to that, but that solution poses high risk of error and is not ideal. I am hoping to get the deserializer functioning as advertised instead.

    Please do let me know what you can do to help. Thanks.

    Best regards,

    Sam Shafer

  • Hi Sam,

    Did you set the CLKIN to the 953 correctly? In RAW10 mode, it should be half the PCLK which is 80MHz/2 = 40MHz?

    Also could you try it on a different 934 system just to rule out the issue with the specific system you are working with.

    Best,

    Jiashow

  • Update: The CLKIN to the 935 is indeed a 40 MHz crystal oscillator. The pixel clock out of the 934 is 80 MHz.

    I will try running the software on another board; that will take a bit to get set up.

  • Update: I ran the software on another board, and got the same results. Solid 10 bit video data out of the 934 with no sign of HYSNC or VSYNC signals on those pins. 

  • Hi Samuel,

    Could you turn off the camera and try enabling patgen on the 953 and see if HSYNC/VSYNC are available? 

    Set 953 registers:

    0xB0 = 0x00

    0xB1 = 0x01

    0xB2 = 0x01

    Best,

    Jiashow

  • Hey Jaishow,

    That did not work. It actually disabled any video out of the deserializer. Maybe I need to change settings on that 934 device as well?

    I also tried the Code Example for Pattern generator from the 935 datasheet, and got the same lack of video or HSYNC:

    WriteI2C(0xB0,0x00) # Indirect Pattern Gen Registers
    WriteI2C(0xB1,0x01) # PGEN_CTL
    WriteI2C(0xB2,0x01)
    WriteI2C(0xB1,0x02) # PGEN_CFG
    WriteI2C(0xB2,0x33)
    WriteI2C(0xB1,0x03) # PGEN_CSI_DI
    WriteI2C(0xB2,0x24) # RGB888
    WriteI2C(0xB1,0x04) # PGEN_LINE_SIZE1
    WriteI2C(0xB2,0x16)
    WriteI2C(0xB1,0x05) # PGEN_LINE_SIZE0
    WriteI2C(0xB2,0x80)
    WriteI2C(0xB1,0x06) # PGEN_BAR_SIZE1
    WriteI2C(0xB2,0x02)
    WriteI2C(0xB1,0x07) # PGEN_BAR_SIZE0
    WriteI2C(0xB2,0xD0)
    WriteI2C(0xB1,0x08) # PGEN_ACT_LPF1
    WriteI2C(0xB2,0x04)
    WriteI2C(0xB1,0x09) # PGEN_ACT_LPF0
    WriteI2C(0xB2,0x38)
    WriteI2C(0xB1,0x0A) # PGEN_TOT_LPF1
    WriteI2C(0xB2,0x04)
    WriteI2C(0xB1,0x0B) # PGEN_TOT_LPF0
    WriteI2C(0xB2,0x65)
    WriteI2C(0xB1,0x0C) # PGEN_LINE_PD1
    WriteI2C(0xB2,0x0B)
    WriteI2C(0xB1,0x0D) # PGEN_LINE_PD0
    WriteI2C(0xB2,0x93)
    WriteI2C(0xB1,0x0E) # PGEN_VBP
    WriteI2C(0xB2,0x21)
    WriteI2C(0xB1,0x0F) # PGEN_VFP
    WriteI2C(0xB2,0x0A)

  • Update: still waiting for the 934 Deserializer to produce HYSNC.

    The Deserializer is outputting valid video data synchronized with the external frame sync signal that is inputted to GPIO0. Yet the HSYNC and VSYNC pins remain idle, HSYNC remaining high and VSYNC reminaing low. They never move.

    I'm surprised that there is seemingly no documentation for how the HSYNC and VSYNC pins generate their respective signals, as it makes debugging those aspects of the system virtually impossible. Any external documents on the subject would be helpful.

    Thanks,

    Sam

  • Hi Sam,

    To enable 935 patgen, you just need to program the following registers in the 935:

    0xB0 = 0x00

    0xB1 = 0x01

    0xB2 = 0x01

    There's no need to program additional registers. Are you saying even using patgen you are not able to see the HSYNC/VSYNC data? Are you not even able to see the data coming from the 934?

  • Hey Jaishow

    That is correct; When I set those registers on the 935, video data doesn't come from the deserializer. HSYNC/VSYNC also doesn't come. The pattern generator is not working. 

    Does the 934 need to be set up for that mode? Otherwise I'm not sure why setting those registers isn't working.

    Any ideas?

    -Sam

  • Hi Sam,

    After more investigation, I don't believe we can support 935 patgen to the 934. It is only supported in CSI mode. What is your CSI throughput into the 935?

    Jiashow

  • Jaishow,

    I'm not exactly sure how to compute/measure that, but here are some values I do know:

    Ref clock (into Serializer): 40 MHz

    Pixel clock (out of Deserializer): 80 MHz

    Operating in RAW10 DVP external clock deserializer mode (backwards compatibility).

    -Sam

  • What's the camera resolution, bits per pixel, and frame rate?

  • Resolution: 800x800

    2 pixels per bit

    60 frames per second

  • HI Samuel,

    Based on your CSI camera requirement, the total CSI bandwidth is only 76.8Mbps, which is lower than the minimum CSI rate requirement for the 935 (80Mbps), even in 1 lane mode. Is there a way to increase the CSI bandwidth?

    Additionally, there's a specific CLKIN frequency you need to meet based on your CSI bandwidth, please refer to the data rate calculation in the app note: http://www.ti.com/lit/an/snla270a/snla270a.pdf. You cannot just use a 40MHz CLKIN.

    Best,

    Jiashow

  • Hey Jaishow,

    This is good to know. Might explain the lack of VSYNC and HSYNC signals.

    I am looking at the application note you provided. It says: RAW10: CSI-2 Throughput = CLKIN × 20

    My CLKIN is 40 MHz, so wouldn't CSI throughput be 800 Mbps? (40 MHz x 20)

    Otherwise I am confused on how to calculate these values. What's a is the best way to increase CSI rate? What is the ideal CLK_IN freq for my application?

    -Sam

  • Hi Sam, 

    Correct. In RAW10 mode, the CSI throughput (total CSI bandwidth in bps) is CLKIN × 20. Your CSI throughput in the 953 needs to match the CSI output of the camera.

    In your application, the total CSI throughput is 76.8Mbps -> If you use CSI one-lane mode, then it would be 76.8Mbps/lane. CLKIN should be 76.8/20 = 3.84MHz. But as I mentioned before, the CSI output from the imager is too low and isn't supported by the 935. You can possibly increase the frame rate or bpp of your camera.

    CSI Throughput = horizontal res * vertical res * bits per pixel * frame rate * some blanking, a percentage.

    Best,

    Jiashow

  • Hey Jaishow,

    I actually gave you an incorrect spec in saying 2 pixels / bit. Actual rate is 10 bits/pixel. That would bring the average CSI throughput up to 384 Mbps.

    Here are my calculations: the sensor is 60 FPS, 800 x 800 resolution, 10 bits per pixel (RAW10)
    Pixel clock: 80 MHz
    CSI-2 data rate: 800 Mb/s
    CSI-2 clock: 400 MHz
    Average data rate: 60 x 800 x 800 x 10 = 384 Mb/s

    I finally was able to get the pattern generator working, after changing most all of the PATGEN config regs. Still no HSYNC/VSYNC present, even with that running and the sensor off.

    What factors into the generation of the those signals from the Deserializer end? Purely CSI-2 protocol? I have never seen those pins move.

    Please do let me know what you can do to help. Really need to get this part of the system working for good video.

    -Sam

  • HI Sam,

    I would recommend just using the sensor. Have you used a different 934? Are they all experiencing the same issue?

    The total CSI throughput is 384Mbps. You would divide this number by the number of lanes you use. And your clock in should be 384Mbps/20.

    Jiashow

  • Jaishow,

    We have two duplicate setups and the same issue has been occurring on both 934 devices. A third setup is being built but we have not tested it yet.

    In regards to the CSI throughput:
    According to www.ti.com/.../snla270a.pdf the CSI-2 throughput is equal to the CSI-2 data rate multiplied by the number of CSI-2 lanes. Our CSI-2 data rate is 800 Mbps and the number of CSI-2 lanes is 1 therefore our CSI-2 throughput is 800 Mbps.

  • HI Samnuel,

    Where did you get that your CSI-2 data rate is 800Mbps? Your clock in should be (384Mbps + blanking%) /20, and your CLKIN can only range between 25MHz to 66.5MHz.

  • Hello Jaishow,

    800 Mbps came from the spec of the sensor, and we've confirmed it via oscilloscope measurement.

    Average data rate: 800 width x 800 height x 10 bits/pixel x 60 FPS = 384 Mbps

    Active percentage: 384 Mbps / 800 Mbps = 48%

    Blanking percentage: 52%

    These values also were verified via scope capture.

    935 reference clock multiplier in backward compatible mode: 20

    935 CSI-2 reference clock required: 800 Mbps / 20 = 40 MHz

    -Sam

  • Hello,

    I was finally able to identify the source of the issue:

    The BISTEN pin was being held high by the FPGA. As soon as I set that pin to be held low, the HSYNC and VSYNC signals appeared exactly as expected.

    Thanks for your help in solving this issue.

    Best regards,

    Sam