DS90UB949-Q1EVM: Data Island transport is not working

Hi Kasagi,

To confirm in your use case, HDMI in on the 949 with audio, I2S out from the 948 (no i2s input on the 949).

On the 948, How many channels of audio are being utilized?  Which pins are you currently utilizing on the EVM?  If using TDM, what are you word lengths?

Which other GPIOs (if any) are currently being utilized on the 949?

Sincerely,
Bryan Kahler

Hi Bryan,

We are using Internal Pre-Programmed EDID and 2-channel HDMI audio.
949 MODE_SEL0 : EDID_SEL =0, AUX_I2S= 0
We are not using TDM. I2S word length is 64.

We are using 8 of GPIO for 949. Setting is as follows.
GPIO0 : 0x0D[3:0] = 0x5 , D_GPIO0 : 0x0D[3:0] = 0x3
GPIO1 : 0x0E[3:0] = 0x3 , D_GPIO1 : 0x0E[3:0] = 0x5
GPIO2 : 0x0E[7:4] = 0x3 , D_GPIO2 : 0x0E[7:4] = 0x3
GPIO3 : 0x0F[3:0] = 0x3 , D_GPIO3 : 0x0F[3:0] = 0x3

We are using 8 of GPIO and I2S signal pins of  948. GPIO Setting is as follows.
GPIO0 : 0x1D[3:0] = 0x3 , D_GPIO0 : 0x1D[3:0] = 0x5
GPIO1 : 0x1E[3:0] = 0x5 , D_GPIO1 : 0x1E[3:0] = 0x3
GPIO2 : 0x1E[7:4] = 0x5 , D_GPIO2 : 0x1E[7:4] = 0x5
GPIO3 : 0x1F[3:0] = 0x5 , D_GPIO3 : 0x1F[3:0] = 0x5
For I2S : MCLK, I2S_CLK, I2S_WC, I2S_DA

Thank you
Kasagi

Hi Kasagi,

Thank you for the information.  Will test a configuration in the lab - please expect an update by EOD 2/5.

Sincerely,
Bryan Kahler

Hi Kasagi,

Could you please send a register dump of the main page for both your 948 and 949?

Sincerely,

Bryan Kahler

Hello Bryan,

I attached the resistor dump files.
(I did not know how to get the port1 resistor setting with one file. These files including port0 resistor setting only.) 

NO I2S signal : 948_DataIsland.nrd, 949_DataIsland.nrd
Wrong GPIO1: 948_forward.nrd, 949_Forward.nrd

Additionally, I confirmed wrong D_GPIO0 signal on Forward Frame transfer mode. 
Some remote GPIO output is not work correctry on Forward Frame transfer mode.

Thnak you
Y.Kasagi

resistor.zip

Hi Kasagi,

Thank you for sending the files.  Will analyze and provide an update tomorrow.

Sincerely,
Bryan Kahler

Hi Kasagi,

Thank you again for providing the files.  I have been able to replicate some of the behavior on this end.  Still investigating the issue.  Please expect another update by EOD Wednesday at the latest.

Sincerely,
Bryan Kahler

Hi Y. Kasagi,

Still investigating this issue on the bench.  To further the investigation, could you please provide the settings for the port0 and port1 registers?

To get the values per port please use 0x1E to control PORT1_SEL or PORT0_SEL prior to reading back the per port registers.

Thank you.

Sincerely,
Bryan Kahler

Hi Y. Kasagi,

We are seeing similar issue on the bench.  Still investigating the issue.  Are there other possible pin mappings for your design or are these pin selections a hard constraint?

Sincerely,

Bryan Kahler  

Hi Bryan,

On our design, we would like to use the 1 of  remote input, 5 of remote output and 2 of High-speed in/out GPIO pins on 948 side.
We confirmed current issue is on GPIO0, GPIO1, DGPIO0 and DGPIO1 of remote output.
I think it is difficult to avoid this issue by pin mapping change. (Temporally, we are currently disabling the wrong GPIO function.) 

Can not use the Dataisland transport for the HDMI audio? 

For the port1 resistor setting, I will send it after duplicating the DGPIO0 issue by using EVM board.

Thank you
Y.Kasagi

Hi Y.Kasagi,

Thank you for the update.  Still looking into this issue with the Data Island Transport and the mapping of choice.

Look forward to the other results.

Sincerely,
Bryan Kahler

Hi Bryan,

I tried to duplicate the DGPIO0 issue, which occured on our system board, by using DS90UB948 EVM board. (MODE_SEL0:S1.5, MODE_SEL1:S1.3)
But, I can't. Because, I don't know why, DGPIO0-3 are not work for the remote GPIO function on our EVM board. (They can work for local GPIO.)
Anyhow, I will wait solution of 1st issue.

And, I found we can't set the DS90UB949 port1 by using remote resistor setting. It can set set form local. (Is this spec?)
We can set the DS90UB948 port1 by using remote resistor setting.

I attached our system board setting for the reference.(changed resistor only) 
We are waiting solution of 1st issue.

Thank you
Y.Kasagi

REGset.zip

On our design, we would like to use the 1 of  remote input, 5 of remote output and 2 of High-speed in/out GPIO pins on 948 side.
We confirmed current issue is on GPIO0, GPIO1, DGPIO0 and DGPIO1 of remote output.
I think it is difficult to avoid this issue by pin mapping change. (Temporally, we are currently disabling the wrong GPIO function.) 

Can not use the Dataisland transport for the HDMI audio? 

For the port1 resistor setting, I will send it after duplicating the DGPIO0 issue by using EVM board.

Thank you
Y.Kasagi

Hi Y.Kasagi,

Thank you for the additional information and confirmation of the issue on GPIO0, GPIO1, DGPIO0 and DGPIO1.  Will review and try to replicate these results in the lab with these settings.

Please expect an update on Wednesday (2/26)

Sincerely,
Bryan Kahler

Hi Y.Kasagi,

I have been able to replicate the issue in the lab, but not have been able to analyze with an active I2S source.  Still looking deeper into this issue.  Please expect another update on Friday.

Sincerely,

Bryan Kahler

Hi Y.Kasagi,

I have replicated your results for data island mode with an active I2S source, but have not yet determined root cause.  Still looking into this issue both on the bench and with the Design team.  

Please expect an update by EOD Wednesday 3/5/2020.

Sincerely,
Bryan Kahler

Hi Y.Kasagi,

Spoke with your FAE today - still working on root cause determination in the lab.

As a test step:

On your 949 in Data island mode please set 0x55[6] = 1 and probe the i2s pins on on the 949.  Are you able to see your data and clocks?

Sincerely,
Bryan Kahler

Hi Bryan,

I confirmed I can see the all of I2S signals on the 949 pin after setting the 0x55[6]=1 with Data Island mode.
But still no Data and WC signals on the 948 side.

Thank you
Y.Kasagi

Hi Y.Kasagi,

We have replication of that as well in the lab.  Still working through this in the lab and with design.  Please expect an update on Wed 3/18.

Sincerely,
Bryan Kahler

Hi Y.Kasagi,

Design has been running simulations on this issue.  Please expect another update on Wed 3/25.\\

Sincerely,
Bryan Kahler

Hi Y. Kasagi,

Still working with design on the issue.  Expecting new simulation results to test on the bench.  Please expect another update by Friday.

Sincerely,
Bryan Kahler

Hi Y. Kasagi,

Still working with design for new simulation results.  Please expect an update on Wednesday.

Sincerely,
Bryan Kahler

Hi Y. Kasagi,

Still working with design for new simulation results.  Please expect an update on Tuesday.

Sincerely,
Bryan Kahler

Hi Y. Kasagi,

Continuing to work with design on new simulation results.  If successful, will test on the bench this Friday.  Will provide another update on Friday.

Sincerely,
Bryan Kahler

Hi Y. Kasagi,

Please try setting bit 6 of register 0x12 in the 948 to 0.

If the issue still persists, please let me know.

Sincerely,
Bryan Kahler

Hello Bryan,

Thank you for your response.

Is this resistor 0x12 means indirect resistor?
(Because, 948 resistor dump value of 0x12 is 0.)

Thank you
Y.Kasagi

Hi Y.Kasagi,

Yes, that setting looks proper.  With that bit not asserted:

On the DS90UB949-Q1, please set register 0x04 to ensure bit 4 is asserted.  Based on the commands being sent, this register should be 0x90.

Sincerely,
Bryan Kahler

Hello Bryan,

Thank you for your response.

I tried to change the resistor value based on your information.
 948 resister value of 0x04 was changed 0xD0 -> 0x90.
 949 resister vaule of 0x12 was changed 0x43 -> 0x03.

But, I can't confirm any improvement.
 Data Island transport mode     : No I2S signal
 Data Forward Channel Frame transport mode  : Wrong GPIO1 output

Please privide the next idea.

Thank you
Y.Kasagi

Hi Y.Kasagi,

Thank you for the feedback.  Could you please describe the HDMI portion of your test setup?  How is the source configured?  Stereo, multi-channel, etc?

Also, in your testing, have you programmed an EDID to the device?

Sincerely,
Bryan Kahler

Hello Bryan,

Thank you for your reply.

For the HDMI setting we only connected the Dell note PC by HDMI cable.
It used Intel chip set for the HDMI.

Regarding EDID program,
we used original Internal pre-programmed EDID for the EVM board.
We used Internal pre-programmed EDID which updated video session only (address 0-0x7F) for our system.
I believe both of audio setting is same audio (2-channel audio) timing profiles.

Thank you
Y.Kasagi

Hi Y.Kasagi,

Thank you for the information.

Our settings should be very closely aligned.

Could you please try with surround sound mode?

Sincerely,
Bryan Kahler

Hello Bryan,

Thank you for your response.

Does your surround sound mode mean the setting of 949 Resister 0x1A bit0?

I tried to change the resister value based on your information.
 948 indirect resister vaule of 0x12 was changed 0x43 -> 0x03.
 949 indirect resister value of 0x04 was changed 0xD0 -> 0x90.
 949 resister 0x1A was changed 0x00 -> 0x01.

But, I can't confirm any improvement.
 Data Island transport mode     : No I2S signal
 Data Forward Channel Frame transport mode  : Wrong GPIO1 output

Could you tell me, if I had misunderstanding.

Thank you
Y.Kasagi

Hi Y.Kasagi,

With respect to modifying the audio portion of the EDID, I'm referring to the audio settings, for example: channel count in the Short Audio Descriptors (SAD).

Sincerely,
Bryan Kahler

Hello Bryan,

Thank you for your response.

I additionally tried to change the EDID as follows.

Channel count in the Short Audio Descriptors (SAD)  : 2ch   (09h)  ->   6ch(0Dh)
Speaker Allocation Data Block                                     : Stereo(01h)  -> 5.1ch(0Fh)
Check sum                                                                    :       (28h)  ->      (16h)

And I changed the HDMI audio mode of PC from Stereo to 5.1ch.
I confirmed the WC frequency was changed. 48KHz -> 44KHz.
Maybe sound mode was correctry changed.

But, no change for the any other.  
Please provide next action.

I would like to confirm these action are for the Data Island transport mode, right?
Did TI changed the EDID to confirm the Data Island transport mode?

Thank you
Y.Kasagi

Hi Y.Kasagi,

Thank you for providing the results of the test.  To confirm, when changing the EDID audio parameters the WC changed to 44 KHz from 48 KHz but data was still not seen on the outputs?

Yes, this is for Data Island Transport Mode.

Sincerely,
Bryan Kahler

Hello Brian,

Thank you for your response.

I confirmed the WC frequency change by using Forward Channel Frame Transport Mode.

I could not confirm any differences of EDID change on the Data Island Transport Mode.

Please provide next action.

Thank you

Y.Kasagi

Hi Y.Kasagi,

Thank you for confirming your results. 

Please try both changes at the same time in Data Island Transport mode

(1) EDID

(2) Settings

Sincerely,

Bryan Kahler

Hello Bryan,

Thank you for your response.

I already tried the both changes (EDID and additional setting) at the same time.

But, I can't see the I2S signal on the Data Island Transport mode.

Is there any resister setting procedure?

I changed the additional setting and transport mode manually after HDMI connection.

Thank you

Y.Kasagi

Hi Y.Kasagi,

These were the potential registers and settings we identified with the design team and simulations.  Working with them now on next steps.  Please expect an update no later than Wednesday.

Sincerely,
Bryan Kahler

Hi Y.Kasagi,

Work is ongoing.  To ensure I'm seeing the same results on this end as you, could you please send me your latest register settings and EDID loaded to SRAM?  

If you believe your test steps vary from ours, they would be helpful as well.

Sincerely,
Bryan Kahler

Hello Bryan,

Thank you for your response.

I attached the Resister setting of the EVM board.
I used "TI 1080p 8ch" of EDID SRAM data.
Result is same as our board.
You can see the indirect resister setting on the file.

Sorry, I sent our system's test result.
Because I could not use the EVM boards by my stay home.

Thank you

Y.Kasagi

949dataisland.zip

Hi Y.Kasagi,

Thank you for sending the register dump.  Have review it and will be testing on the lab setup.  Please expect an update by EOD Wednesday.

As for next steps, what are your testing capabilities from the house?  Are you able to read the indirect registers?  If possible, please remote in and dump the remote registers.  If unable to use ALP over remote connection, please let me know.

Sincerely,
Bryan Kahler

Hello Bryan,

Thank you for your response.

>As for next steps, what are your testing capabilities from the house?

I already in my company's laboratory.
 
>Are you able to read the indirect registers? 

Yes, I can read the indirect register.

>If possible, please remote in and dump the remote registers. 

Is this means, I will get the all of indirect registors value of EVM boards (949 and 948), right?
How is the address range of indirect register? 00h-FFh?

Thank you
Y.Kasagi

Hi Y.Kasagi,

The main registers on page 0 may be accessed directly, 0x00 - 0xFF.

The indirect registers are accessed by first changing the page (using 0x40, ANA_IA_SEL) and then indirect reads (using 0x41 and 0x42).

Sincerely,
Bryan Kahler

Hello Bryan,

Thank you for your response.

>The indirect registers are accessed by first changing the page (using 0x40, ANA_IA_SEL)
>and then indirect reads (using 0x41 and 0x42).

I would like to confirm regarding Analog resistor read.
(1) This function is only for the 949, right? (I will get the register data of 949 only.)
(2) Which is the target registers,  HDMI registers, FPD3 TX registers or both?
(3) How about the Analog register offset range to get the data? 00h-FFh?
(4) Is ALP have a function to get the all of Analog register data? If it have please inform to me.

Thank you
Y.Kasagi

Hi Y.Kasagi,

Both devices have multiple pages.  If a register isn't located on the main page, indirect access is required.

To perform the read of an indirect register (register on another page) the general flow is:

Write to 0x40 to set the page, auto increment, etc...

then access through that page:

Write to 0x41 to set the indirect register to be read

Read to 0x42 to read the value of that register indicated the prior write to 0x41

Reading the full range from 0x00 to 0xFF should be okay.

ALP does have this functionality - It has a register tab and an indirect register tab.  Click on the indirect register tab and then select the page of interest from the drop down menu.

Sincerely,
Bryan Kahler

Hello Bryan,

Thank you for your response.

I have got the dump of 949 indirect registers by using 0x40 - 0x42 register and out 948 board.
Please review them.

I would like to confirm for the following previous requested register setting.
I used the registers (0x66 PGIA and 0x67 PGID) for these indirect setting. Is this correct?
If it is wrong, please inform me the correct registers.
 
 948 indirect register vaule of 0x12 was changed 0x43 -> 0x03.
 949 indirect register value of 0x04 was changed 0xD0 -> 0x90.

Thank you
Y.Kasagi

Summary.zip

Hey Y.Kasagi,

In the previous posts I don't see anywhere mentioned that you should be adjusting indirect registers 0x12 or 0x04. Those were supposed to be main page registers that Bryan was referring to. 

Best Regards,

Casey