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SN75DP130: Interchanging Lanes in Main Link

Part Number: SN75DP130

Hi,

We have a Cyclone 10 GX based custom board with SN75DP130 re-driver and a mDP connector. We are trying to port Altera's DP IP in TX-Only mode. Because of schematic issues, XCVR lanes form FPGA are connected in the reverse order i.e., lane_0 from FPGA is connected to IN3 on re-driver (polarity is not inverted). We are using DP breakout boards between FPGA board and Monitor to properly map lane order. 

I am trying to bring up DP_TX in single lane mode. HPD is working fine, link training is happening properly on AUX channel. But the DP_TX IP is going into VIDEO_IDLE mode instead of NORMAL_VIDEO mode. If IN0-IN2 are not actively driven and only IN3 is driven, does SN75DP propagate it on OUT3?

Regards

Bhargav

  • Bhargav

    You have to use I2C to disable link training and manually enable all lanes when connecting lane 0 to IN3 of DP130.

    Thanks

    David

  • Thanks for your time.

    >> You have to use I2C to disable link training and manually enable all lanes when connecting lane 0 to IN3 of DP130.

    Does it mean that only IN3 of SN75DP is getting enabled in my case? 

    If I configure DP_TX in 4-lane mode (but the order going to SN75DP will be in reverse. i.e, tx[0] -> IN3 and tx[3] -> IN0) and appropriately re-order the lane at the monitor/display end, will default link training work?

    The datasheet has register descriptions but not any example programming sequences. Can you please let me know where I can find example sequences?

    Regards

    Bhargav

  • Bhargav

    If DP130 link training is enabled and only one DP lane is enabled, DP130 will only enable DP0 and disable DP1, 2, and 3. If lane 0 is connected to DP3, you have to disable the link training and manually enable DP3. 

    4 lane would still work as long as the lane order is the same on the input and the output of the DP130.

    For SW example, please use this app note as a starting point: http://www.ti.com/lit/an/slla349/slla349.pdf.

    Thanks
    David

  • Hi David,

    I am still using 1-lane DP_TX and connected it to IN0 of SN75DP130. Link training is enabled. When I look at DP130 register values before and after link training, they look fine. But still monitor goes into sleep (power saving) mode. Can you please let me know if the register values are fine?

    Some DP130 registers (0x01 to 0x17) have default values.

    Register Address Before Link Training After Link Training
    0x19 0x04 0x14
    0x1A 0x01 0x00
    0x100 0x1 0x1
    0x101 0x0 0x1
    0x103 0x0 0x1
    0x104 0x0 0x0
    0x105 0x0 0x0
    0x106 0x0 0x0
    0x600 0x0 0x0

    Regards

    Bhargav

  • Bhargav

    Does DP 4-lane mode works? If DP 4 lane mode works, would you please dump out both the DPCD and I2C registers?

    Could you please check HPD_SNK and HPD_SRC? Are they staying high or low? 

    What is the condition for the FPGA to go into the VIDEO_IDLE mode?

    Thanks

    David

  • Hi David,

    Thanks for all the support.

    The behavior is same with 4-lane mode too. HPD coming to FPGA is high, Link Training is successful and monitor going to idle state.

    HPD_SNK and HPD_SRC are high throughout the experiment.

    I have raised a query on Altera Forum to understand what drives DP_Source IP into VIDEO_IDLE mode.

    Register

    Address

    Before

    Link Training

    After

    Link Training

    0x1  0x1 0x1
    0x2  0x0 0x0
    0x3  0x1 0x12
    0x4  0x4 0x4
    0x5  0x0 0x0
    0x6  0x0 0x0
    0x7  0x0 0x0
    0x8  0x0 0x0
    0x9  0x0 0x0
    0xa  0x0 0x0
    0xb  0x0 0x0
    0xc  0x0 0x0
    0xd  0x0 0x0
    0xe  0x0 0x0
    0xf  0x0 0x0
    0x10 0x0 0x0
    0x11 0x0 0x0
    0x12 0x0 0x0
    0x13 0x0 0x0
    0x14 0x0 0x0
    0x15 0x8 0x8
    0x16 0x8 0x8
    0x17 0x0 0x0
    0x18 0x0 0x0
    0x19 0x4 0x14
    0x1a 0x0 0x0
    0x100 0x1 0x1
    0x101 0x0 0xf
    0x103 0x0 0x1
    0x104 0x0 0x1
    0x105 0x0 0x1
    0x106 0x0 0x1
    0x600 0x0 0x0
    0x101 0x0 0xf

    Regards

    Bhargav

  • Hi David,

    When we started probing the DP_TX IP core status deeper, we found that the main link is not up consistently. Whenever the link goes down, the IP is going into VIDEO_IDLE mode. When the link goes up, IP transits from VIDOE_IDLE mode to NORMAL_VIDEO mode, but it does not stay there for long to view the video on monitor. Are there similar registers in SN75DP130 that denote the main link status?

    Regards

    Bhargav

  • Bhargav

    DP130 does not report main link status. 

    Can the FPGA read the DPCD register 0x00202h, 0x00203h, 0x00204h, and 0x00205h? These are the registers sink uses to report the status of the link training.

    Can you also disable DP130 squelch (register 0x03h) to see if the link is able to stay up? 

    Thanks

    David

  • Hi David,

    Sorry for the delayed response. DPCD registers 0x00202 - 0x00205 are always 0. Disabling squelch did not have any effect. 

    Regards

    Bhargav

  • Bhargav

    If the sink DPCD register 0x00202 - 0x00205 reads back as 0, then the link training is not successful. 

    Do you have a DPA-400 or an AUX snoop tool that can look at the AUX traffic?

    Thanks

    David

  • Hi David,

     We do not have any external AUX snoop tool. We are using Altera generated example design, which has an option for printing the AUX commands during link training. The AUX command log matches with that of a working design on a Altera Development board.

    Attaching AUX Command log for your reference.

    Do registers 0x00202-0x00205 get updated only at the end of link training or get updated periodically?

    Regards

    Bhargav

    00000000 [SRC] Req sent AUX_RD @ 0201 (DEVICE_SERVICE_IRQ_VECTOR) 90 02 01 00
    00000661 [SRC] Reply got AUX_ACK 00 00
    00000142 [SRC] Req sent AUX_RD @ 0218 (TEST_REQUEST) 90 02 18 00
    00000661 [SRC] Reply got AUX_ACK 00 00
    00000158 [SRC] Req sent I2C_WR MOT=1 40 00 50 00 00
    00000641 [SRC] Reply got AUX_ACK|I2C_ACK 00
    00000133 [SRC] Req sent I2C_RD MOT=1 50 00 50 0F
    00000625 [SRC] Reply got AUX_ACK|I2C_ACK 00 00 FF FF FF FF FF FF 00 10 AC B8 A0 53 57 48 32
    00000417 [SRC] Req sent I2C_RD MOT=1 50 00 50 0F
    00000625 [SRC] Reply got AUX_ACK|I2C_ACK 00 2D 1C 01 04 A5 34 20 78 3A 04 95 A9 55 4D 9D 26
    00000418 [SRC] Req sent I2C_RD MOT=1 50 00 50 0F
    00000625 [SRC] Reply got AUX_ACK|I2C_ACK 00 10 50 54 A5 4B 00 71 4F 81 80 A9 40 D1 C0 D1 00
    00000418 [SRC] Req sent I2C_RD MOT=1 50 00 50 0F
    00000625 [SRC] Reply got AUX_ACK|I2C_ACK 00 01 01 01 01 01 01 28 3C 80 A0 70 B0 23 40 30 20
    00000417 [SRC] Req sent I2C_RD MOT=1 50 00 50 0F
    00000625 [SRC] Reply got AUX_ACK|I2C_ACK 00 36 00 06 44 21 00 00 1E 00 00 00 FF 00 56 57 36
    00000419 [SRC] Req sent I2C_RD MOT=1 50 00 50 0F
    00000625 [SRC] Reply got AUX_ACK|I2C_ACK 00 31 31 38 42 38 32 48 57 53 0A 00 00 00 FC 00 44
    00000418 [SRC] Req sent I2C_RD MOT=1 50 00 50 0F
    00000625 [SRC] Reply got AUX_ACK|I2C_ACK 00 45 4C 4C 20 55 32 34 31 35 0A 20 20 00 00 00 FD
    00000418 [SRC] Req sent I2C_RD MOT=0 10 00 50 0F
    00000625 [SRC] Reply got AUX_ACK|I2C_ACK 00 00 31 3D 1E 53 11 00 0A 20 20 20 20 20 20 01 DE
    00000429 [SRC] Req sent I2C_WR MOT=1 40 00 50 00 80
    00000641 [SRC] Reply got AUX_ACK|I2C_ACK 00
    00000133 [SRC] Req sent I2C_RD MOT=1 50 00 50 0F
    00000625 [SRC] Reply got AUX_ACK|I2C_ACK 00 02 03 1C F1 4F 90 05 04 03 02 07 16 01 14 1F 12
    00000417 [SRC] Req sent I2C_RD MOT=1 50 00 50 0F
    00000625 [SRC] Reply got AUX_ACK|I2C_ACK 00 13 20 21 22 23 09 07 07 83 01 00 00 02 3A 80 18
    00000417 [SRC] Req sent I2C_RD MOT=1 50 00 50 0F
    00000625 [SRC] Reply got AUX_ACK|I2C_ACK 00 71 38 2D 40 58 2C 45 00 06 44 21 00 00 1E 01 1D
    00000418 [SRC] Req sent I2C_RD MOT=1 50 00 50 0F
    00000625 [SRC] Reply got AUX_ACK|I2C_ACK 00 80 18 71 1C 16 20 58 2C 25 00 06 44 21 00 00 9E
    00000418 [SRC] Req sent I2C_RD MOT=1 50 00 50 0F
    00000625 [SRC] Reply got AUX_ACK|I2C_ACK 00 01 1D 00 72 51 D0 1E 20 6E 28 55 00 06 44 21 00
    00000418 [SRC] Req sent I2C_RD MOT=1 50 00 50 0F
    00000625 [SRC] Reply got AUX_ACK|I2C_ACK 00 00 1E 8C 0A D0 8A 20 E0 2D 10 10 3E 96 00 06 44
    00000418 [SRC] Req sent I2C_RD MOT=1 50 00 50 0F
    00000625 [SRC] Reply got AUX_ACK|I2C_ACK 00 21 00 00 18 00 00 00 00 00 00 00 00 00 00 00 00
    00000417 [SRC] Req sent I2C_RD MOT=0 10 00 50 0F
    00000625 [SRC] Reply got AUX_ACK|I2C_ACK 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0C
    00000430 [SRC] Req sent AUX_RD @ 000E ( ) 90 00 0E 00
    00000661 [SRC] Reply got AUX_ACK 00 00
    00000144 [SRC] Req sent AUX_RD @ 0000 (DPCD_REV) 90 00 00 0E
    00000661 [SRC] Reply got AUX_ACK 00 11 0A 84 01 01 00 01 80 02 00 06 00 00 00 00
    00000383 [SRC] Req sent AUX_RD @ 0200 (SINK_COUNT) 90 02 00 00
    00000661 [SRC] Reply got AUX_ACK 00 41
    00000157 [SRC] Req sent AUX_WR @ 0600 (DPCD) 80 06 00 00 02
    00000677 [SRC] Reply got AUX_ACK 00
    00000135 [SRC] Req sent AUX_WR @ 0600 (DPCD) 80 06 00 00 01
    00000677 [SRC] Reply got AUX_DEFER 20
    00000113 [SRC] Req sent AUX_WR @ 0600 (DPCD) 80 06 00 00 01
    00000677 [SRC] Reply got AUX_ACK 00
    00000125 [SRC] Req sent AUX_WR @ 0100 (LINK_BW_SET) 80 01 00 00 0A
    00000677 [SRC] Reply got AUX_DEFER 20
    00000114 [SRC] Req sent AUX_WR @ 0100 (LINK_BW_SET) 80 01 00 00 0A
    00000677 [SRC] Reply got AUX_ACK 00
    00000129 [SRC] Req sent AUX_WR @ 0101 (LANE_COUNT_SET) 80 01 01 00 81
    00000677 [SRC] Reply got AUX_DEFER 20
    00000113 [SRC] Req sent AUX_WR @ 0101 (LANE_COUNT_SET) 80 01 01 00 81
    00000677 [SRC] Reply got AUX_ACK 00
    00000122 [SRC] Req sent AUX_RD @ 0107 (DOWNSPREAD_CTRL) 90 01 07 00
    00000661 [SRC] Reply got AUX_DEFER 20
    00000110 [SRC] Req sent AUX_RD @ 0107 (DOWNSPREAD_CTRL) 90 01 07 00
    00000661 [SRC] Reply got AUX_ACK 00 00
    00000145 [SRC] Req sent AUX_WR @ 0107 (DOWNSPREAD_CTRL) 80 01 07 00 00
    00000677 [SRC] Reply got AUX_ACK 00
    00000136 [SRC] Req sent AUX_WR @ 0102 (TRAINING_PATTERN_SET) 80 01 02 04 21 00 00 00 00
    00000741 [SRC] Reply got AUX_DEFER 20
    00000118 [SRC] Req sent AUX_WR @ 0102 (TRAINING_PATTERN_SET) 80 01 02 04 21 00 00 00 00
    00000741 [SRC] Reply got AUX_ACK 00
    00000160 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 01
    00000661 [SRC] Reply got AUX_DEFER 20
    00000111 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 01
    00000661 [SRC] Reply got AUX_ACK 00 00 00
    00000160 [SRC] Req sent AUX_RD @ 0206 (ADJUST_REQUEST_LANE0_1) 90 02 06 01
    00000661 [SRC] Reply got AUX_ACK 00 01 00
    00000188 [SRC] Req sent AUX_WR @ 0103 (TRAINING_LANE0_SET) 80 01 03 03 01 00 00 00
    00000725 [SRC] Reply got AUX_ACK 00
    00000238 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 01
    00000661 [SRC] Reply got AUX_DEFER 20
    00000111 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 01
    00000661 [SRC] Reply got AUX_ACK 00 01 00
    00000161 [SRC] Req sent AUX_RD @ 0206 (ADJUST_REQUEST_LANE0_1) 90 02 06 01
    00000661 [SRC] Reply got AUX_ACK 00 01 00
    00000175 [SRC] Req sent AUX_WR @ 0102 (TRAINING_PATTERN_SET) 80 01 02 04 22 01 00 00 00
    00000741 [SRC] Reply got AUX_ACK 00
    00000833 [SRC] Req sent AUX_RD @ 0202 (LANE0_1_STATUS) 90 02 02 01
    00000661 [SRC] Reply got AUX_ACK 00 07 00
    00000159 [SRC] Req sent AUX_RD @ 0206 (ADJUST_REQUEST_LANE0_1) 90 02 06 01
    00000661 [SRC] Reply got AUX_ACK 00 01 00
    00000167 [SRC] Req sent AUX_WR @ 0102 (TRAINING_PATTERN_SET) 80 01 02 00 00
    00000677 [SRC] Reply got AUX_ACK 00

  • Bhargav

    Registers 0x00202-0x00205 get updated periodically, this is the command "Req sent AUX_RD @202" and response is in the "AUX_ACK".

    Looking at the log file, the link training for one lane is successful as the read back value is 0x07. 

    Thanks

    David

  • Hi David,

    Thanks for the support. The log was for a x1 configuration. Altera's DP core provides APIs for checking the main link status. When I tried to poll the link status, for very short duration the link becomes active and for the rest of the time, the link is down.

    I am suspecting SI issues relating to XCVRs on our custom board could be the reason. Is there a way to confirm that?

    Regards

    Bhargav

  • Bhargav

    You would need a high bandwidth scope, and preferably one with the DP compliance SW install, to check for the signal integrity.

    The DP link training has two parts, the first part is the clock recovery phase and second part is the main link equalization training phase. When the link is down, do you see either phase failed the link training? Can you send me a log file with link down?

    Thanks

    David