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DS90UB949-Q1: Screen Displays Vertical Lines

Part Number: DS90UB949-Q1

Hello,

We are using the DS90UB949 on our own PCB to talk to a DS90UB948 inside a customer screen module. While the display works fine most of the time, we sometimes get a series of vertical lines appearing across the screen. These lines appear to be spaced every other pixel and the pattern spans the entire width of the screen. We've been attempting to debug to no avail, but here's what we have found out:

1. The vertical lines can be triggered in multiple ways: resetting the screen module, resetting the 949, setting the HDMI Digital Reset bit, unplugging the HDMI cable and plugging it back in.

2. The DUAL_STS register (0x5A) in the 949 reads as 0xCD (the expected value), indicating that the problem doesn't seem to involve the deserializer link or the HDMI clock frequency.

3. When the Pattern Generator is enabled using the External Clock while the vertical lines are on the screen, they remain there for any pattern selected. However, if the Pattern Generator is set up to use the Internal Clock, the lines never appear on the screen - even if they were previously there on the HDMI signal.

This all points to there being some kind of problem with the HDMI clock, but none of the status registers I've read so far show any issues detecting it. The HDMI frequency is reading as 156 MHz, which is expected for the 1920x1200 resolution we're dealing with.

Please let me know if there is any additional information I can provide to help resolve this issue.

Thanks,
Josh

  • Hi Joshua,

    What PATGEN settings are you using during the internal and external clock source?

    Regards,

    Michael W.

  • Internal timing w/ Internal Pixel Clock:

    PGCDC1 = 0x02

    PGAFS1 = 0x80

    PGAFS2 = 0x07

    PGAFS3 = 0x4B

    PGTFS1 = 0x20

    PGTFS2 = 0x38

    PGTFS3 = 0x4D

    PGHBP = 0x50

    PGVBP = 0x1A

    PGHSW = 0x20

    PGVSW = 0x06

    PBSC = 0x02

    Pattern Generator Configuration Register 0x65 = 0x05 for Internal Clock, Autoscroll On

    Pattern Generator Control Register 0x64 = 0x01 for Patgen On

    In this mode, the vertical lines will NOT appear on the generated patterns

    Internal Timing w/ External Pixel Clock:

    Indirectly-mapped registers and Register 0x64 set the same as above, Register 0x65  = 0x0D

    In this mode, the vertical lines will appear on the generated patterns

    External Timing w/ External Pixel Clock:

    Indirectly-mapped registers and Register 0x64 set the same as above, Register 0x65 = 0x01

    In this mode, the vertical lines will appear on the generated patterns

  • Hi Joshua,

    can you read the value of the pixel clock that the 948 is reading in these cases? I want to see if the DES is reading a incorrect pixel clock value.

    Regards,

    Michael W.

  • Hi Michael,

    I used the Frequency Count register (0x1B) to read the pixel clock as follows:

    First, I wrote 0x0C to the FC register

    Then, I read the value of the FC register

    I also read the General Status register (0x1C), just to be thorough.

    I went through this process for each of the three cases, and the results are as follows:

    Case 1, Normal HDMI:

    FC register gives 0x5A, which should correspond to a frequency of 150 MHz if I did my math right

    GS register gives 0x3B

    The results are the same whether there are lines showing on the screen or not

    Case 2, Patgen with External Timing & Pixel Clock:

    Results are the same as Case 1, whether there are lines showing on the screen or not

    Case 3, Patgen with Internal Timing & Pixel Clock:

    FC register gives 0x38, which should correspond to a frequency of 93.3 MHz

    GS register gives 0x3B

    As mentioned previously the lines don't appear with these settings

    Case 4, Patgen with Internal Timing & External Pixel Clock:

    FC register gives 0x59, which should correspond to a frequency of 148.3 MHz 

    GS register gives 0x3B

    The results are the same whether there are lines showing on the screen or not

  • Hi Joshua,

    I am going to send you a friend request can you send me you your display datasheet and your 949 layout of your board.

    Regards,

    Michael W.

  • Hi Michael,

    I've sent over the Altium design files for the board. Unfortunately, I don't have the display datasheet but I attached the timing information for it. Please let me know if you receive them properly.

    Thanks,

    Josh

  • Hi Michael,

    Have you had the opportunity to review the information I sent? Please let me know if you've been able to make any progress.

    Thanks,

    Josh

  • Hi Josh,

    Sorry for the delay, I do not see anything obviously wrong with your schematic or layout. What is the HDMI source? can you try a different HDMI source? 

    Regards,

    Michael W.

  • Hi Michael,

    We've already switched around the HDMI source several different ways, unfortunately. The problem definitely follows the board, not the HDMI source or the display module. A board which displays the vertical lines will display them with any source and display combination we've tried.

    Thanks,

    Josh

  • Hi Josh,

    One reason this could be happening is that the 949 might be be incorrectly in single mode, can you try forcing the 949 into dual mode by writing a 1 to the FORCE_DUAL register to see if this fixes the issue.

    Regards,

    Michael W.

  • Hi Michael,

    If that were the case, wouldn't reading the DUAL_STS register give an incorrect value? As I mentioned in the original post, this register has a value of 0xCD when I read it, which indicates the 949 is in dual link mode.

    Unfortunately right now my state is locked down so I don't have access to my setup. Once I'm able to go in to the office again I can give the FORCE_DUAL bit a try to see if it fixes the problem.

    Thanks,

    Josh

  • Hi Josh,

    I agree with you that it seems like it is in dual mode but the issue makes sense that it would be in single mode some how.

    here is a more detailed sequence to try:

    Set Reg0x1E=0x02 (Select Port1 in Port Select register)

    Set Reg0x20=0x8F (Make Port1 Dual link capable in Deserializer Capabilities register)

    Set Reg0x1E=0x01 (Select Port0 in Port Select register to restore the register default value)

    Set Reg0x5B[2:0]=011b

    Regards,

    Michael W.

  • Hi Michael,

    Thank you for the suggestion. I'll be sure to update this post when I'm able to try it out.

    Thanks,

    Josh

  • Hi Michael,

    Good news: I was able to set up a webcam so that I can observe the screen remotely so that I could try out the suggested sequence of register settings. Unfortunately, it did not fix the issue. I observe no change to the vertical lines on the display after forcing it into dual link mode.

    Thanks,

    Josh

  • Hi Josh,

    Can you substitute your board for a DS90UB949-Q1EVM and see if the issue persists?

    Regards,

    Michael W. 

  • Hi Michael,

    The issue went away when I tried substituting the EVM. As a note, the vertical lines don't appear with every PCB we spin. Only about one in twenty boards seems to have this problem.

    Thanks,

    Josh

  • Hi Josh,

    On the board that is having the issue, can you try to input a lower PCLK for the video? Like reduce the FPS? if it works with reduced PCLK then we know this is a signal integrity issue.

    Regards,

    Michael W.

  • Hi Michael,

    I lowered the refresh rate from 60 Hz to 30 Hz and it seems to have worked. The vertical lines don't appear no matter how many times I reset the HDMI circuitry on the serializer. Once I'm back in the office I'll be able to test it more thoroughly to make sure the problem is really gone, but I think it's safe to assume that this is a signal integrity issue.

    The only question now is where the problem is happening on the board. The serializer doesn't seem to think anything is amiss- it says it can detect a valid HDMI clock, and the serdes link is also reading as stable. I'd appreciate any advice you can offer.

    Thanks,

    Josh

  • Hi Josh,

    Since we know it is a signal integrity issue, we should figure out if it is a FPD-Link Signal issue or a HDMI/DP++ issue. we can do this by running a BIST on the link between the 949 and the DES to determine if FPD-Link is the issue.

    Regards,

    Michael W.

  • Hi Michael,

    Can you give an example sequence of register writes/reads to perform a BIST? I'm working remotely so I don't have access to the IC pins. I've managed to enable the BIST by writing 0x01 to DES Register 0x24, but trying to turn the BIST off by writing 0x00 to the same register gives me a communications error. Does the I2C bridge no longer operate in BIST mode?

    Thanks,

    Josh

  • Hi Josh,

    The BIST disables the I2C across the forward channel and back channel so you will need to locally write to the DES.

    Regards,

    Michael W.