This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS110DF410: Appropriate register settings

Part Number: DS110DF410

Dear Technical Support Team,

 

I have been debugging for CDR unlocked issue with DS110DF410.

 

Questions:

1.) Could you share the appropriate setting for 11.0957Gbps?

According to 8.4.4 Standards-Based Modes, the procedure is as follow.

I'd like to know correct register setting each steps for not Standards-Based Modes such as 11.0957Gbps.

Especially register from 0x60 to 0x63(PPM count as NPPM = 11.0957 × 1280 = 14202.496?) and register 0x2f(table 2).

 

1. Select the desired channel of the DS110DF410 by writing the appropriate value to register 0xff.

2. Set bits 5:4 of register 0x36 to a value of 2'b11 as described above to enable the 25 MHz reference clock.

3. Write registers 0x2f, and 0x36 with the correct values.

4. Compute the expected PPM count values for Group 0 and Group 1 as described above.

5. Write the expected PPM count values into registers 0x60-0x63 as described above, setting bit 7 of both

registers 0x61 and 0x63.

6. Set the value 0xff into register 0x64 for an approximate PPM count tolerance of 1100-1400 PPM.

7. Reset the retimer CDR by setting and then clearing bits 3:2 of register 0x0a.

 

2.) If I need to change more registers than 1.) , could you share it?

 

3.) If DS110DF410 is not suitable for 11.0957Gbps, could you introduce other retimer products?

 

【Connections】

Optical signal ⇒ SFP ⇒ CDR ⇒ LSI

 

【Issues】

If optical cable is under 60km, CDR locked. However more than 60km, CDR doesn't lock.

 

Channel Registers 0x02 shows below

 

Locked case:0xDC

Unlocked case:repeat the value 0x04 and 0x00

 

【Current CDR register settings】

Related CDR register setting is as follow.

Other registers are default setting.

 

■Rate Setting

Channel Register            

 

0x2F: 0xD4

0x60: 0x7B

0x61: 0xB7

0x62: 0x7B

0x63: 0xB7

0x64: 0xFF

 

■CTLE and DFE Adpt Mode

Channel Register            

0x31: 0x60

 

■Other settings

Channel Register

0x1E: 0xE1

 

Best Regards,

ttd

  • Hi, see my inputs below.

    1. Could you share the appropriate setting for 11.0957Gbps?
      • 0x60 = 0x7A
      • 0x61 =  0xB7
      • 0x62 = 0x7A
      • 0x63 = 0xB7
      • 0x64 = 0xFF
    2. If I need to change more registers than 1.) , could you share it?
      • No other registers needed for CDR rate configuration
    3. If DS110DF410 is not suitable for 11.0957Gbps, could you introduce other retimer products
      • DS110DF410 fully supports 11.0957Gbps in retimed mode. max rate per datasheet is 11.3Gbps
    4. Feedback on customer settings
      • CDR rate settings are close to mine. Customer should use 0x7A instead of 0x7B for 0x60 and 0x62
      • I recommend that adapt mode 2 be used instead, by setting 0x31 = 0x40

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer

    1. aaa

  • Hi Rodrigo Natal,

    Thank you for your reply.

     

    ・Is this 0x2F register correct for 11.0957Gbps?

     0x2F: 0xD4

    ・What is the benefit of MODE2 compared wih MODE3?

     I think that MODE3 need to wait until CTLE Locked. So if CTLE unlocked due to jitter, DS110DF410 doesn't go next step(DFE).

     Unfortunately CDR doesn't lock with MODE2(0x31 = 0x40).

    ・Tried bypass CDR 

      When bypass CDR, FRAMER of LSI synchronized input serial data. 

      Optical signal ⇒ SFP ⇒ DS110DF410(bypass CDR) ⇒ LSI

    ・Tried to change VCO LPF DAC

       Change Reg 0x1F from 0x55 to 0x57 and Reg 0x09 bit6 stay 0(not change 1).

       Then CDR is locked(0x02:0xDC)

       However LSI caused low bit error.

     According to datasheet , this register for PRBS. Is it valid setting to lock CDR or not recommend?

       Attached txt is all register setting.

       

    register.txt
    Address	Data
    000	00
    001	00
    002	DC
    003	00
    004	00
    005	00
    006	00
    007	00
    008	00
    009	00
    00A	10
    00B	0F
    00C	08
    00D	00
    00E	93
    00F	69
    010	3A
    011	20
    012	A0
    013	30
    014	00
    015	10
    016	7A
    017	36
    018	00
    019	23
    01A	00
    01B	03
    01C	24
    01D	00
    01E	E1
    01F	57
    020	00
    021	00
    022	00
    023	40
    024	00
    025	00
    026	00
    027	10
    028	30
    029	00
    02A	30
    02B	00
    02C	72
    02D	80
    02E	00
    02F	C6
    030	00
    031	60
    032	11
    033	88
    034	BF
    035	1F
    036	31
    037	00
    038	10
    039	00
    03A	A5
    03B	00
    03C	00
    03D	00
    03E	80
    03F	00
    040	00
    041	01
    042	04
    043	10
    044	40
    045	08
    046	02
    047	80
    048	03
    049	0C
    04A	30
    04B	41
    04C	50
    04D	C0
    04E	60
    04F	90
    050	88
    051	82
    052	A0
    053	46
    054	52
    055	8C
    056	B0
    057	C8
    058	57
    059	5D
    05A	69
    05B	75
    05C	D5
    05D	99
    05E	96
    05F	A5
    060	7B
    061	B7
    062	7B
    063	B7
    064	FF
    065	00
    066	00
    067	20
    068	00
    069	0A
    06A	44
    06B	00
    06C	00
    06D	00
    06E	00
    06F	00
    070	03
    071	02
    072	03
    073	10
    074	10
    075	10
    076	B0
    077	C8
    078	57
    079	5D
    07A	69
    07B	75
    07C	D5
    07D	99
    07E	96
    07F	A5
    

       

    ・RX EYE 

       Attached EYE Patter on RX when 60km.

      EYE is very narrow. How do you think about it? Is it possible to open EYE through DS110DF410? 

    60km_RX_EYE.pptx

    Best Regards,

    ttd

  • Hi Rodrigo Natal,

    I added  register.txt and 60km_RX_EYE.pptx above previous post.

    Could you check it?

    Best Regards,

    ttd

  • Hi, my inputs below.

    • Related to "RX_EYE" you shared, the TI retimer is suitable for use in very long reach optical transceiver applications. You may refer the application note per link below which I wrote. As per the application note the DS110DF410 can handle low eye height signal coming from the SFP+ optical transceiver electrical output

    • Related to retimer Rx adapt modes, both adapt mode 2 and adapt mode 3 have CTLE adaption gated by CDR lock. The only difference is that for adapt mode 2 the CTLE is further optimized after CDR is locked while in adapt mode 3 the CTLE is not tuned further after CDR acquires lock. So, it does not make any sense to me why you would see no CDR lock with adapt mode 2 but then observe CDR lock with adapt mode 3
    • You are stating that  setting 0x1F=0x57 with 0x09[6]=0 allows CDR lock to occure. However, 0x1F[4:0] should not have any effect when 0x09[6]=0. Thus, this data point does not make sense either
    • I reviewed the register values. The retimer eye opening values being observed are below our recommended minimum thresholds. I would suggest the following experiments
    • Try setting retimer to adapt mode 2 (0x31 = 0x40) but manually override the CTLE boost setting by setting 0x2D[3]=1. Once this override is enabled you may manually force CTLE boost via channel register 0x03. Try channel register 0x03 values of 0x01, 0x04 and 0x10
    • Try enabling the CTLE limiting output mode (EQ_LIMIT-EN)  to see if performance is improved. This is done by setting channel register 0x13[2]=1

  • Hi,

     Q1)

    >I reviewed the register values. The retimer eye opening values being observed are below our recommended minimum thresholds

    I think this is observed from the value of 0x27 (HEO) and 0x28 (VEO).

    Could you tell me the recommendation value for HEO and VEO?

    If the value is below recommendation value, is it difficult to lock CDR?

     

    Q2)

    DS110DF410 has 4 CDRs and ch1 is used as TX and ch2 as RX.

    It has the following configuration in my design.

     

    Ch1(TX):  Framer ⇒ CDR (ch1) ⇒ SFP +

    Ch2(RX):   SFP + ⇒ CDR (ch2) ⇒ Framer

     

    The dump data I sent yesterday was Ch2 data.

     

    The value of 0x27 / 28 on Ch1 (TX) side was as follows.

    0x27 HEO: 0.828 UI

    0x28 VEO: 422 mV

     

    Values are calculated from the formula of SNLA323 Table 21. Read HEO and VEO

     

    How much margin does this value have with respect to the standard value?

    ■dump register  file

    tx0(ch_1).txt
    Address	Data
    0000	00
    0001	00
    0002	DC
    0003	01
    0004	00
    0005	00
    0006	00
    0007	00
    0008	00
    0009	00
    000A	10
    000B	0F
    000C	08
    000D	00
    000E	93
    000F	69
    0010	3A
    0011	20
    0012	A0
    0013	34
    0014	00
    0015	10
    0016	7A
    0017	36
    0018	40
    0019	23
    001A	00
    001B	03
    001C	24
    001D	00
    001E	E1
    001F	54
    0020	00
    0021	00
    0022	00
    0023	40
    0024	00
    0025	00
    0026	00
    0027	35
    0028	87
    0029	40
    002A	30
    002B	00
    002C	72
    002D	80
    002E	00
    002F	C6
    0030	00
    0031	60
    0032	11
    0033	88
    0034	BF
    0035	1F
    0036	31
    0037	01
    0038	10
    0039	00
    003A	A5
    003B	00
    003C	00
    003D	00
    003E	80
    003F	00
    0040	00
    0041	01
    0042	04
    0043	10
    0044	40
    0045	08
    0046	02
    0047	80
    0048	03
    0049	0C
    004A	30
    004B	41
    004C	50
    004D	C0
    004E	60
    004F	90
    0050	88
    0051	82
    0052	A0
    0053	46
    0054	52
    0055	8C
    0056	B0
    0057	C8
    0058	57
    0059	5D
    005A	69
    005B	75
    005C	D5
    005D	99
    005E	96
    005F	A5
    0060	7A
    0061	B7
    0062	7A
    0063	B7
    0064	FF
    0065	00
    0066	00
    0067	20
    0068	00
    0069	0A
    006A	44
    006B	00
    006C	00
    006D	00
    006E	00
    006F	00
    0070	03
    0071	04
    0072	01
    0073	10
    0074	10
    0075	10
    0076	B0
    0077	C8
    0078	57
    0079	5D
    007A	69
    007B	75
    007C	D5
    007D	99
    007E	96
    007F	A5
    

    rx0(ch_2).txt
    Address	Data
    0000	00
    0001	00
    0002	DC
    0003	01
    0004	00
    0005	00
    0006	00
    0007	00
    0008	00
    0009	00
    000A	10
    000B	0F
    000C	08
    000D	00
    000E	93
    000F	69
    0010	3A
    0011	20
    0012	A0
    0013	34
    0014	00
    0015	10
    0016	7A
    0017	36
    0018	40
    0019	23
    001A	00
    001B	03
    001C	24
    001D	00
    001E	E1
    001F	54
    0020	00
    0021	00
    0022	00
    0023	40
    0024	00
    0025	00
    0026	00
    0027	10
    0028	3E
    0029	20
    002A	30
    002B	00
    002C	72
    002D	80
    002E	00
    002F	C6
    0030	00
    0031	40
    0032	11
    0033	88
    0034	BF
    0035	1F
    0036	31
    0037	01
    0038	10
    0039	00
    003A	A5
    003B	00
    003C	00
    003D	00
    003E	80
    003F	00
    0040	00
    0041	01
    0042	04
    0043	10
    0044	40
    0045	08
    0046	02
    0047	80
    0048	03
    0049	0C
    004A	30
    004B	41
    004C	50
    004D	C0
    004E	60
    004F	90
    0050	88
    0051	82
    0052	A0
    0053	46
    0054	52
    0055	8C
    0056	B0
    0057	C8
    0058	57
    0059	5D
    005A	69
    005B	75
    005C	D5
    005D	99
    005E	96
    005F	A5
    0060	7A
    0061	B7
    0062	7A
    0063	B7
    0064	FF
    0065	00
    0066	00
    0067	20
    0068	00
    0069	0A
    006A	44
    006B	00
    006C	00
    006D	00
    006E	00
    006F	00
    0070	03
    0071	00
    0072	10
    0073	10
    0074	10
    0075	12
    0076	B0
    0077	C8
    0078	57
    0079	5D
    007A	69
    007B	75
    007C	D5
    007D	99
    007E	96
    007F	A5
    

    Best Regards,

    ttd

    1. I reviewed the register values. The retimer eye opening values being observed are below our recommended minimum thresholdsI think this is observed from the value of 0x27 (HEO) and 0x28 (VEO). Could you tell me the recommendation value for HEO and VEO? If the value is below recommendation value, is it difficult to lock CDR
    • Yes, 0x27 and 0x28 contain the HEO and VEO
    • TI recommended minimum thresholds are HEO greater or equal to 0.4UI and VEO greater or equal to 200mV
    • Correct, bad eye opening performance will affect CDR lock performance
    • The value of 0x27 / 28 on Ch1 (TX) side was as follows: 0x27 HEO: 0.828 UI 0x28 VEO: 422 mV. How much margin does this value have with respect to the standard value
      • These eye values are very good, and have great margin to the above minimum threshold values

     

     

     

  • Hi,

    Thank you for your reply.

    I calculated HEO and VEO for RX. These are under recommendation value you said "HEO greater or equal to 0.4UI and VEO greater or equal to 200mV"

             HEO_UI = Reg_0x27 / 64 = 0x10 / 64 = 0.25UI

             VEO_mV = Reg_0x28 * 3.125 = 3E * 3.125 = 193.75mV

    I will try your two advice below.

    • Try setting retimer to adapt mode 2 (0x31 = 0x40) but manually override the CTLE boost setting by setting 0x2D[3]=1. Once this override is enabled you may manually force CTLE boost via channel register 0x03. Try channel register 0x03 values of 0x01, 0x04 and 0x10
    • Try enabling the CTLE limiting output mode (EQ_LIMIT-EN)  to see if performance is improved. This is done by setting channel register 0x13[2]=1
    • Try setting retimer to adapt mode 2 (0x31 = 0x40) but manually override the CTLE boost setting by setting 0x2D[3]=1. Once this override is enabled you may manually force CTLE boost via channel register 0x03. Try channel register 0x03 values of 0x01, 0x04 and 0x10
    • Try enabling the CTLE limiting output mode (EQ_LIMIT-EN)  to see if performance is improved. This is done by setting channel register 0x13[2]=1

    Best Regards,

    ttd

  • Hi,

    >TI recommended minimum thresholds are HEO greater or equal to 0.4UI and VEO greater or equal to 200mV

    The recommended value for the Eye opening is recognized as the value after passing through the DFE.
    Is it possible to teach the recommended value of the Eye opening at the front stage of CTLE (CDR input terminal)?

    • Try setting retimer to adapt mode 2 (0x31 = 0x40) but manually override the CTLE boost setting by setting 0x2D[3]=1. Once this override is enabled you may manually force CTLE boost via channel register 0x03. Try channel register 0x03 values of 0x01, 0x04 and 0x10

            ⇒I tried and no improvement.

    • Try enabling the CTLE limiting output mode (EQ_LIMIT-EN)  to see if performance is improved. This is done by setting channel register 0x13[2]=1

            ⇒

                HEO: improve 0.1UI

                VEO:improve 50~60mVp-p

    Best Regards,

    ttd

  • Hi,

    At this point I would speculate that there may be some signal over-equalization issue happening for the retimer channel in question. See TI recommended procedure below for over-EQ case.

    • For some applications (such as a port side one like SFP+) the host PCB channel may be very short.
    • However, the host or module Tx driver might implement by default a high amount of preemphasis. Such a condition can result in an overequalized signal at the input of retimer
    • Excessive input overequalization can potentially lead to CDR lock issues
    • The retimer CTLE can be forced to lowest boost setting to improve lock performance for overEQ case
    • In addition, the DFE can be used to mitigate the effect of overEQ by setting it to apply attenuation via tap 1

    Suggested operations for overEQ scenario

    I. CTLE configuration

    REG    Value    Comment

    0x31    0x00      Set Adapt mode 0

    0x2D    0x88     Enable EQ override

    0x03     0x00     Set EQ = 00

    0x3A    0x00     Set EQ = 00

    0x0A    0x1C     Puts the CDR into RESET

    0x0A   0x10       Releases the CDR from reset

    II. DFE tap 1 optimization procedure

    REG    Value    Comment

    0x1E    0xE1     Enable DFE

    0x12[7]   0            Set DFE tap 1 polarity to 0

    Loop for optimizing the DFE attenuation setting

    REG       Value       Comment

    0x12[4:0]  0x020x1A   Set DFE tap 1 to desired weight

    0x0A       0x1C         Puts the CDR into RESET

    0x0A       0x10         Releases the CDR from reset

    0x02[4]     Read CDR lock status

    0x27         Read HEO

    0x28         Read VEO

    Note: It is recommended to allow for ~20ms wait time after implementing a CDR reset and release operation


  • Hi 

    I'm trying your recommendation steps for over EQ .

    I will feedback later about that.

    by the way ,I'd like to check following situation again.

    >You are stating that  setting 0x1F=0x57 with 0x09[6]=0 allows CDR lock to occure. However, 0x1F[4:0] should not have >any effect when 0x09[6]=0. Thus, this data point does not make sense either


    The range of 0x1F is 0 to 31, and the default value is 0x55.
    If the above is the VCO control voltage, the resolution for the corresponding rate 8.5 to 11.3 [Gbps] is
    2.8 [Gbps] / 31 = 0.09032, 0x55 becomes 8.5 [Gbps] + 0x55 * 0.09032
    = 10.39677 [Gbps].

    As a way of thinking, is there any difference in the above recognition?



    If I set 0x1F without setting 1 to the OV bit (0x09 [6]),
    Will PLL operation start based on the set value?
    (Without transition to free-run mode)



    In the setting state of ①, when transition to free run mode,
    What kind of setting should be performed to return to the normal PLL mode?



    Whether the current setting status is normal mode (PLL mode) or free-run mode
    Is there a register to determine?



    As we have developed so far, our actual machine, when 0x1F: 0x50
    Lock is performed for 11.0957 [Gbps] rate, but 0x1F: 0x55 (default setting)
    At the time of Lock was not done.

    The configuration is as follows.

    Framer (OTU2e) ⇒ CDR ⇒ SFP + ⇒ (SMF: 80 [km])
                 ⇒ SFP + ⇒ CDR (Loss Of Lock) ⇒ Framer (OTU2e)


    Could you give us any thoughts on the possible causes of such an event?
    (Poor high frequency characteristics of substrate, wavelength dispersion due to transmission line 80 [km], etc.)

    Attach the register dump data for Lock OK / NG.



    In the actual machine, with the above configuration, 0x1F: 0x50 (RX CDR only),
    Lock is performed for 10.709 [Gbps] rate,
    Is it locked even in free run mode?

    Best Regards,

    ttd

  • Hi,

    I'd rather not address these follow up questions yet, as I do not believe they are relevant to issue at hand. Specifically, the TI DS110DF410 retimer by design can achieve CDR lock to either 11.0957gbps or 10.709Gbps as long as channel registers 0x60 through 0x63 are programmed correctly and input signal characteristics are within specified device tolerance. The customer should not need to program the VCO control voltage (loop filter voltage) or other PLL parameters manually.

    Let's await the results of evaluation with my recommended EQ settings and see whether CDR lock performance is improved.

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer

  • Hi,

    Thank you for your reply.

    >Let's await the results of evaluation with my recommended EQ settings and see whether CDR lock >performance is improved.

    ⇒I tried your EQ settings and  CDR locked. I have some questions.

    ・In the case of Adpt Mode (Reg 0x1F: 0x40 or 0x60), then it was not automatically applied to the EQ adjustment value for your recommend EQ setting(over-EQ) . Why?

    ・HEO / VEO recommended value. Is this value only the recommended value for CDR LOCK?

       Is this specified and included for BER of latter LSI ?
    (  (HEO ≧ 0.4 [UI], VEO ≧ 200 [mVp-p] guarantees BER-12 at 10GbE rate, etc.)

    ・At present, it seems to be locked below the recommended value(HEO ≧ 0.4 [UI], VEO ≧ 200 [mVp-p] g), 

      Is it possible to submit a value of  the minimum required HEO / VEO for CDR lock?

    Best Regards,

    ttd

  • Hi, see my inputs below.

    • In the case of Adpt Mode (Reg 0x1F: 0x40 or 0x60), then it was not automatically applied to the EQ adjustment value for your recommend EQ setting(over-EQ) . Why?
    • These settings assume adapt mode 0 is being used. if you use adapt mode 1 or 2 instead then CTLE and DFE override bits need to be enabled prior to manual configuration of their values
    • HEO / VEO recommended value. Is this value only the recommended value for CDR LOCK?
    • Both CDR lock and error free operation
    • At present, it seems to be locked below the recommended value(HEO ≧ 0.4 [UI], VEO ≧ 200 [mVp-p] g), Is it possible to submit a value of  the minimum required HEO / VEO for CDR lock?
      • The HEO/VEO lock thresholds may be configured by the user via channel register
      • For default setting, VEO lock threshold is 2. As LSB step size is 4 counts of VEO, this is equal to 2*4*3.125mV = 25mV
      • For default setting the HEO lock threshold is 2. As LSB step size is 4 counts of HEO, this is equal to 2*4*(1/64)UI = 0.125UI

     

    Address

    (Hex)

    BITS

    DEFAULT VALUE (Hex)

    MODE

    EEPROM

    FIELD NAME

    DESCRIPTION

    6A

    7

    0

    RW

    Y

    VEO_LCK_THRSH3

    VEO threshold to meet before lock is established. The LSB step size is 4 counts of VEO.

    6

    0

    RW

    Y

    VEO_LCK_THRSH2

    5

    1

    RW

    Y

    VEO_LCK_THRSH1

    4

    0

    RW

    Y

    VEO_LCK_THRSH0

    3

    0

    RW

    Y

    HEO_LCK_THRSH3

    HEO threshold to meet before lock is established. The LSB step size is 4 counts of VEO.

    2

    0

    RW

    Y

    HEO_LCK_THRSH2

    1

    1

    RW

    Y

    HEO_LCK_THRSH1

    0

    0

    RW

    Y

    HEO_LCK_THRSH0