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TL16C2552: Is it okay to supply clock with jitter?

Hung Ching Hsu
Expert 3086 points
Part Number: TL16C2552

Hi

Let me have a question about TL16C2552.

My customer wants to know whether is there any problem on operation, if a clock with the jitter inputs to TL16C2552, 

The details are as follows.

We are currently studying clock supply to the TL16C2552 using the following route.

Oscillator ⇒ FPGA (internal PLL) ⇒ TL16C2552

From the jitter performance of the output terminal of the FPGA, the clock frequency input to the TL16C2552 is
targeting to 3.072MHz and it is expected to be 2.96MHz (min), 3.071672MHz (typ), 3.191348MHz (max).
We are going to use TL16C2552  at a baud rate of 9600bps. (So internal 20 division)

After checking the data sheet, there was no description about the specifications for the input clock (accuracy, frequency width, Duty, etc.)

So could you tell me whether is there any problem on operation, if a clock with the jitter inputs to TL16C2552?

Regards, 

Jo

  • 0
    TI__Guru 62910 points

    Hi Joe,

    This may work, but it is outside what the device was intended to support. Having an accurate reference frequency is important in ensuring that effective baud rate differences between transmitting and receiving nodes are minimal. The device can support some small frequency errors, but these would typically be within a narrower range like you would expect from a crystal oscillator. For reference, the device was validated to support clock drifts of 100 ppm.

    Regards,

    Max