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DS90UB948-Q1: Maximum amounts of GPIO pair (947/948 communication)

Roy Chou1
Genius 12565 points
Part Number: DS90UB948-Q1

Hi Team,

I would like to know the maximum amounts of GPIO pair. And these GPIO could communicate two way(947 to 948 and 948 to 947)

I found below GPIO showing in datasheet.

947          948

GPIO0        GPIO0

GPIO1        GPIO1

GPIO2        GPIO2

GPIO3        GPIO3

D_GPIO0    D_GPIO0 (high speed)

D_GPIO1    D_GPIO0 (high speed)

D_GPIO2    D_GPIO0 (high speed)

D_GPIO3    D_GPIO0 (high speed)

Is there 8 GPIO pairs could be use? 

One thing I would like to know is the speed limitation for GPIO. Because our customer would like to send the PWM signal via GPIO and wouldn't like to have large delay. Could you tell me how to calculate the speed limitation?  

  • 0
    TI__Mastermind 19720 points

    Hi Roy,

    Each GPIO can only be an input or output. Each GPIO can only be mapped to their corresponding pin on the connected SER, so GPIO0 can only be mapped to GPIO0 and D_GPIO3 can only be mapped to D_GPIO3. Are you asking about the latency of the GPIO's or the bandwidth of the GPIO's?

    Regards,

    Michael W.

  • 0 in reply to Michael.Walker
    TI__Genius 12565 points

    Hi Michael,

    Sorry, I have typo in my question.

    1. first question is How many GPIO could be mapped to their corresponding pin?

    Is there "8" GPIO could be mapped to their corresponding pin? GPIO0~3 and D_GPIO0~3 right?

    2. I would like to know the latency calculation and bandwidth of each GPIO

    3. For register only GPIO, what is the latency from 947 to 948 (if I use I2C to transmit the signal from ECU) 

    Thank you 

    Roy

  • 0 in reply to Roy Chou1
    TI__Mastermind 19720 points

    Hi Roy,

    1. If you are using Dual FPD-Link then the 8 GPIO's can be mapped to their corresponding pins.

    2. This depends on the PCLK(or FPD-Link Rate) and if you are using them in forward channel or back channel.

    3. Again, the PCLK is needed for this information.

    Regards,

    Michael W.

  • 0 in reply to Michael.Walker
    TI__Genius 12565 points

    Hi Machael,

    If I set PCLK=96MHz (dual link), could you provide me the formula calculation about

    1. forward channel : latency calculation and bandwidth of each GPIO

    2. back channel : latency calculation and bandwidth of each GPIO

    3. For register only GPIO, what is the latency from 947 to 948 (if I use I2C to transmit the signal from ECU) 

    If there is any condition should be set, like PCLK, could you help set a normal value and calculate above value?

    Regards,

    Roy

  • 0 in reply to Roy Chou1
    TI__Mastermind 19720 points

    Hi Roy,

    For the forward channel GPIO's they are sampled at your PCLK Frequency in single link mode or half of your PCLK Frequency in dual link. So you GPIO sample speed will be 96MHz/2 =48MHz. We recommend that you try to pass a signal that is no faster than 1/4 of the sampling speed. So the max Effective GPIO frequency will be 12MHz. The Forward channel GPIO Latency is described in the datasheet of the SER the 948 is connected to. 

    The Back Channel GPIO frequency will be dependent on the Back Channel Frequency, please look in Table 3 on the 948 datasheet.

    Regards,

    Michael W.

  • 0 in reply to Michael.Walker
    TI__Genius 12565 points

    Hi Michael,

    Thank you for your comments.

    Regards,

    Roy