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SN65DP159: HDMI output does not appear

Part Number: SN65DP159

We are evaluating a prototype board equipped with SN65DP159, but the output is not recognized properly.

Symptoms: HDMI signal does not appear ( 'Signal Error' is displayed on the monitor, but only the signal frequencies are recognized )

Signal: 3840x2160 59.94Hz

Monitor: EIZO EV2785

We use this device on the products, so we designs according to past design data. Something is wrong but we can not find it.

We found that especially the DC level of TX2+ is very low, and we think this may be the cause.( Please refer to the attached file. )

Do you know why this happens?

/cfs-file/__key/communityserver-discussions-components-files/138/SN65DP159_5F00_TX.xlsx

  • Hi

    1. Can you please send the full schematic? Part of the DP159 connection is cut off in the spreadsheet.

    2. Are you seeing this issue on multiple boards or just one board?

    3 Have you tried to re-flow the DP159 or the HDMI connector? Does re-flow solve the issue?

    3. Can you please dump out the full DP159 registers, both Page 0 and Page 1? To access Page 1, please write 0x01 to register 0xFFh first, and then dump from 0x00h to 0xB1h.

    Thanks
    David

  • Thank for your reply, David-san.

    1. Can you please send the full schematic? Part of the DP159 connection is cut off in the spreadsheet.

    We are sorry that we can not show you the full schematic because of out corporate compliance. (Because everyone can see it.)

    The attached schematic shows the HDMI output section and I think other part is very simple. #3,#13,#14,#36,#38,#39 pins are connected to a FPGA, and #21-#30,#32,#33 pins are connected to a I/O connctor.

    2. Are you seeing this issue on multiple boards or just one board?

    We tested two boards and with different monitors, and they behave the same.

    3 Have you tried to re-flow the DP159 or the HDMI connector? Does re-flow solve the issue?

    No. But we tested two boards.

    3. Can you please dump out the full DP159 registers, both Page 0 and Page 1? To access Page 1, please write 0x01 to register 0xFFh first, and then dump from 0x00h to 0xB1h.

    Please refer to the following attached file.

    /cfs-file/__key/communityserver-discussions-components-files/138/dp159_5F00_registers.txt

    Best regards,

    Yoshiyuki Nakashima

  • Nakashima-san

    For 4k@60Hz, Page 0 register 0x0Bh TX_TERM_CTL should be set to 0x11 (75 -150ohm termination), and TMDS_CLOCK_RATIO_STATUS should be set to 1. 

    You can refer to this app note for the DP159 I2C configuration setting: http://www.ti.com/lit/an/slla468/slla468.pdf.

    Thanks

    David

  • David-san

    We have tried some registers to change and we could not solve this issue.

    But we found the abnormal DC level issue is not caused by this device, and we think this device has no problem.

    Now we check the FPGA (TMDS Tx IP).

    Thank you for your supports.

    Best regards,

    Yoshiyuki Nakashima