• Resolved

DP83867IR: TX Interface skew between different input types as it relates to timing

Prodigy 80 points

Replies: 13

Views: 115

Part Number: DP83867IR

Hello,

I am seeing around 200 pS of skew between signals that comprise the TX interface in signal integrity simulations. The signals are tightly matched and extracted using HFSS. This skew, I believe, is due to most signals having GPI inputs while the TX_D0 and TX_D1 signals have a GPIO_SGMII_IN input buffer. I haven't done any timing analysis at this point but am concerned that 200 pS removed from the overall margin may be significant. Does anyone have any experience with this concern?

Regards,

Steve