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PCA9306: Component in short circuit

Part Number:

Hello the community,

I'm facing an issue with the PCA9306 on some products.

One eight board I investigated, I found the PCA9306 with a low impedance between clock and data input/output.

It read the datasheet many times and I thought there is a problem with our schematics:

We use it in that way:

And it seems it will be preferable to use it with the 5V on VREF2 to respect the datasheet statement saying that VREF1 must not be higher than VREF2.

I'm I right ?

What is the exact consequences with our design ? It seems it works on many products a long time (product sold since 4 years now)...

Thanks in advance for your lights.

  • Sorry, the picture were not visible. I put it in attached file.

  • Corentin Bonneau said:

    Part Number: PCA9306

    Hello the community,

    I'm facing an issue with the PCA9306 on some products.

    One eight board I investigated, I found the PCA9306 with a low impedance between clock and data input/output.

    It read the datasheet many times and I thought there is a problem with our schematics:

    We use it in that way:

    And it seems it will be preferable to use it with the 5V on VREF2 to respect the datasheet statement saying that VREF1 must not be higher than VREF2.

    I'm I right ?

    What is the exact consequences with our design ? It seems it works on many products a long time (product sold since 4 years now)...

    [Bobby] The consequence would be that the 'ViL' for the device is now lower. So essentially you've done 2 things, (1) slow down your prop delay and (2) gave yourself a lower ViL. {I use ViL loosely here as this is not the real name for the parameter, what I mean is side x will follow side y once it is below 'ViL'}

    In actuality, this lower ViL you have has very little effect on the signal integrity. Prop delays elongation is likely in the double digit nanosecond range and since you aren't operating at a super low Vcc level like 1.8V or lower the foot room you have for ViL should be more than enough.

    Getting to the point here, swapping the higher voltage rail for the lower voltage rail on Vref1 and Vref2 should NOT result in damage to the device and only generates mild differences in operation that shouldn't matter at ~482kHz operating frequency.

    Thanks in advance for your lights.

    From what I can see, there shouldn't be damage occurring to the PCA9306 device based on the schematic. The device itself is actually pretty robust compared to most I2C devices when we look at the absolute max IoL it can handle (128mA) so I rarely see this device get damaged from an over current event.

    May I ask what is connected to both sides of the PCA9306? (any I2C buffers? Cabling? Anything that someone could touch and zap with ESD?)

    -Bobby

  • Hello Bobby and thanks for your help.

    So I understand in your explenations that swapping our voltage rails will not really improving the robustess of the PCA.

    But It will improve the low voltage level and the propagation delay.

    On the 5V side, there is a FireWire cable of 1 meter which is connected to another board containing an another PCA9306 (I joined schematics).

    On the 3.3V, we have I2C components as bus extender, touch screen driver, LED driver.

    You advise to re-inforced ESD protections on our schematic ?

  • Sorry I made a mistake in the pictures posted. Below you see the intire schematic of my first post:

  • Corentin Bonneau said:

    Hello Bobby and thanks for your help.

    So I understand in your explenations that swapping our voltage rails will not really improving the robustess of the PCA.

    But It will improve the low voltage level and the propagation delay.

    On the 5V side, there is a FireWire cable of 1 meter which is connected to another board containing an another PCA9306 (I joined schematics).

    [Bobby] So the 1 meter cable may potentially be a source for something called inductive kickback which I have seen damage our devices before. Can you get scope shots of the communication on the cable sides with the cable connected and communicating? We would want to see from the master cable side and receiver cable side for any undershooting.

    On the 3.3V, we have I2C components as bus extender, touch screen driver, LED driver.

    [Bobby] When you say bus extender, are you talking about an I2C buffer/repeater or an I2C switch?

    You advise to re-inforced ESD protections on our schematic ?

    [Bobby] At the moment, I'm just making an assumption the damage could have come from ESD if the copper traces were handled without proper ESD protection.

    -Bobby

  • Hello Bobby,

    Thanks again for your help.

    I will get the traces requested next Thuesday.

    I also imaging that there is a possibility of 12V short to the I2C bus due to their proximity in the cable if the cable is thorn in bad direction. Adding resistors should be enough in order to protect the I2C lines (assuming there are ESD diodes between SDA/SDC signal and the Vref rail inside the components ?)

    Have a good week-end.

  • Hello Bobby,

    Below you can see scope trace for SDA slave side:

    SCK slave side:

    SCK master side:

    SDA master side:

    Thanks.

  • I forget to answer to one of your previous question:

    [Bobby] When you say bus extender, are you talking about an I2C buffer/repeater or an I2C switch?

     


    I talk about I2C GPIO bus expander PCF8575.

    Have a good day.

  • "Adding resistors should be enough in order to protect the I2C lines (assuming there are ESD diodes between SDA/SDC signal and the Vref rail inside the components ?)"

    Correct. we do have ESD cells on our Vref/SDA/SCL lines. Our datasheet seems to spec that if you go below the absolute max ratings and conduct one of the clamping diodes (from the ESD cell), you should limit the current to less than 50mA.

    The SDA Master waveform on the falling edge seens to take some dips slightly below GND. Can you redo all the waveform shots and zoom in one on falling transaction with very high resolution and sampling? We want to see if the signal may be undershooting too far. I imagine this could damage the device in a way that does not damage the actual pass FETs....

    Thanks,

    -Bobby

  • Hello Bobby,

    Thanks again for your help.

    Correct for the undershoot on SDA.

    I take new scope traces below.

    SDA master side:

    SDA slave side:

    SCK slave side:

    SCK master side:

    It seems we don't reach the negative clamping voltage of -1,2V, but I'm not really fond of this ring effect.

    In the same way as overshoot, adding resistor can protect the device in the case we go below -Vclamp, right ?

    Have a good day.

  • It looks like the datasheet's absolute maximum ratings for the I/O pins (meaning the SDA/SCL lines) is down to -0.5V. This undershooting could damage the device seeing as it looks fairly close to the limit here.

    "In the same way as overshoot, adding resistor can protect the device in the case we go below -Vclamp, right ?"

    Correct, by adding a small dampening resistor,  infront of whatever is driving this line low we can slow down the di/dt and limit the undershooting effect. Adding some cap could also help but since I2C limits the max cap value this should probably be avoided. I would try adding a 20 ohm series resistor infront of the driver who is pulling low on the SDA_master scope shot. If you have control of the pull down strength of the master, you could also make it weaker.

    -Bobby

  • Hello Bobby,

    Thanks for your help it was really interesting.

    I'll try adding resistors and add scope traces to give you a feedback.

    Have a good day.

    -Corentin

  • Hello Bobby,

    Here below is an update after adding resitor on SDA and SCK slave side.

    For SDA no resistor :

    For SDA with 30 ohm:

    For SCK with no resistor:

    For SCK with 140 ohm:

    The 140 ohm correspond to value in order to protect the IC againt 12V short: 12V-5V / 0.05A = 140 ohm.

    Another tests show that on SDA if I put a resistor above 500 ohm, I loose I2C component on the bus. For SCK it starts to 800 ohm.

    So it seems that a resistor of 220ohm to handle 12V short should be usable.

    Do you think this value could be different after swaping the Vref rail ?

    Thanks in advance for your help and have a good day.

  • Hey Corentin,

    I was going through my assigned threads and saw I missed your reply. My apologies on the delay.

    The series resistance will shift up the VoL of the I2C bus which could become greater than the ViL of the devices on the bus so using very large values could disrupt I2C communication like you saw. Changing the Vref value (assuming Vref shares the same power rail as the slaves on the bus) would change the acceptable max resistance value since ViL scales with Vcc due to the I2C spec (ViL=30% of Vcc) though at the same time the VoL caused by the series resistor will also shift up because you shift the Vcc (VoL=Rseries*IoL where you will be shifting Vcc up so IoL will scale up too).

    From your scope shot, it looks like the series resistor will be able to provide the protection required for you system.

    -Bobby

  • Hi Bobby,

    Thanks for your answer. Don't worry about the delay, I'll redesign the board in September,

    I just told about reverting the component in order to follow the datasheet statement that Vref2 must be greater than Vref1. So I'll conserved the 5V on master side and 3.3V and slave side but master I²C signals will arrive on SDA/SCL2 pins instead of SDA/SCL1 and my question was if there is a possible impact on my previous results.

    So I understand from your answer that if I'm not changing the Vref voltage, there is no impact.

    Thanks again Bobby, I tick the resolve issue box.

    Hope you enjoyed or will enjoy your summer holidays soon.

    Corentin