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Part Number: ONET1130EC
I have some other questions about thermal compensation in ONET1130EC. This part is not fully described, so there are no clear understanding. As you can see there are 2 bits TXTCSELx present in register 11 corresponded for thermal compensation.
But there are no description about available values and influence on ONET1130EC. So can you clarify next questions:
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Sorry for the delay in response. Here are my responses to your questions on the thermal compensation:
It’s correct that it’s temperature compensation of modulation signal amplitude?
Response: Yes, the TXTCSEL[1:0] bits of the Register 11 control how well the signal amplitude is maintained by compensating for the temperature dependent variations in the amplitude.
How compensation mechanism are implemented? It’s just additional coefficients or something another?
Response: Temperature compensation is implemented through a feedback loop inside the gain stages of the driver, by controlling the coefficients that define the extent of constant gain or constant amplitude of the output signal.
What are combinations of bits can be set and what does they means?
Response: There are 4 levels of temperature compensation feature that can be applied to the signal, through the TXTCSEL[1:0] bits of Register 11. Unfortunately we do not have the exact quantification of what the individual levels mean at a systems level, but setting the TXTCSEL[1:0] to 2'b11 will apply the highest temperature compensation to the signal. The default value for these select bits TXTCSEL[1:0] is however 2'b00, which applies a moderate compensation. Please note that setting the select bits TXTCSEL[1:0] to 2'b01 results in the least compensation.
Hope that helps.
In reply to Sriharsha Kota Pavan:
Correction in my reply to your last question above:
"Unfortunately we do not have the exact quantification of what the individual levels mean at a systems level, but setting the TXTCSEL[1:0] to 2'b11 will apply the lowest temperature compensation to the signal. The default value for these select bits TXTCSEL[1:0] is 2'b00, which applies a moderate compensation. Setting the select bits TXTCSEL[1:0] to 2'b01 results in the highest compensation."
In reply to Vladimir Aparin:
On the CDR bandwidth settings of ONET1130EC :
The bits [5:7] of Register 51 are provided for allowing the user to specify the CDR bandwidth at both Tx and Rx side. The CDR bandwidth is nothing but the bandwidth of the Jitter transfer properties of the CDR device and hence is a measure of the signal tracking capabilities of the device CDR. For 10Gbit/s Datacom applications, it is recommended to have a CDR bandwidth as high as 4.5MHz.
The exact settings of the bits [5:7] of Register 51 in ONET1130EC correspond to an internal resistor value that can be tuned anywhere between 75ohm (corresponding to Reg 51 [5:7] of 000) to 600ohm (corresponding to Reg 51 [5:7] of 111). The lowest setting corresponds to a CDR jitter transfer bandwidth of 3MHz, while the highest setting corresponds to a CDR bandwidth of 8MHz. The default Register setting of 010 corresponds to a CDR jitter transfer bandwidth of 4.5MHz.
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