I have a PC board schematic that uses TLK1102E. I would like the design to be verified by TI. The block diagram in MS-WORD has been attached for reference.
Please find attached tlk1102_bloc.doc
Looks good to me. I assume this is some sort of cable tester and board 2 is just a loopback. Otherwise you could move the device in what you call TX on board 2 because it's receive equalization is stronger than the transmit de-empasis. I2C control is recommended for fine tuning capabilities.
The outputs of the device should be ac coupled as well. If the qsfp cable does not contain ac coupling caps you might want to put them on the board. 100nF are fine for 10GE.
Thanks for your reply and the suggestions .The design is a Bit Error Rate tester , which evaluates the next generation Physical layer devices . In this context , board no.2 is identical to board no.1. So we will be testing board to board traffic of 40 Gbps across Cu and Optical cable assemblies. The pattern generation and checking of received data will be implemented in the FPGA with SERDES logic.
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