ONET8501V application question

Hello,

My name is Sriharsha, I will be happy to help you with your question. 

The FLT is triggered only when one of the following three conditions prevail in the ONET8501V chip:

1. Voltage at MONB exceeds the voltage at RZTC (1.16V),

2. Photodiode current exceeds 150% of its set value, or

3. Bias control DAC drops in value by more than 50% in one step.

To understand which of these conditions apply in your case, I will need more information on the specifics: Is it the input differential signal line you're referring to in your post? I'm not sure I understand what you mean by adding the modulation signal to the differential signal line. Please clarify. Also, what voltage are you changing that impacts the phenomenon?

Thanks,

Sri

Dear  Sriharsha
Thank you for your great support, the Customer is validating as you suggest.
Another problem need your help: My customer meet 1pcs abnormal Chip of ONET8501V, which VCC short to GND, the FA gave the conclusion as follows: Electrical overstress (EOS) damage was responsible for this failure return.
Now the customer require to explain what cause EOS damage？ Voltage or Current？ And how much is the Amplitude? I explain that maybe caused by ESD, but the customer is not satisfied with the answer. By the way, the costumer fcst is 120K/M.

Hello,

Could you help to provide the FA report number (the QTS #) that you are refering to so I may review your inquiry? 

Regards,

Billy Buniak

 Dear Buniak,

      The FA report number is :QTS_400968-1,Thank you very much!

Thank you.  The FA report shows EOS damage at the VCC/GND circuit.  The results of the FA alone cannot determine the exact cause of the EOS event, there are various possible causes that can lead to EOS depending on the customer application and test/manufacturing environment.   

Please reference the datasheet for the Voltage /Current rating for this device. Note that the maximum Voltage rating for VCC is 4V:  http://www.ti.com/lit/ds/symlink/onet8501v.pdf

TI recommends that the customer evaluate the application environment for sources of transient or steady-state Electrical Overstress. Detailed analysis and measurement of the customer’s board environment and the customer’s test environment will be required to identify the specific cause of EOS.

It is recommended that the following best practices be incorporated into board / system assembly and test flows and board / system design to avoid future cases of EOS.

Application Parameters:

•  Perform measurements of the application system, both under operating conditions and under testing conditions:

  • Confirm application complies with all Absolute Maximum Ratings and Recommended Operating Conditions in the datasheet (including voltage, current, timing, and temperature measurements);

  • Confirm power sequencing datasheet requirements are followed for each device in the application;

  • Confirm datasheet ramp rate requirements are followed for each device in the application;

  • Confirm that nodes on the board are operating at the intended voltage;

• • Specifically, confirm that pairs of nodes that are intended to be at the same potential are at the same potential;

• • Confirm power supply lines and signal lines are free of excessive noise;

  • Confirm power supply lines and signal lines are free of voltage spikes (positive or negative).    

Test Flow:

• Avoid hot switching:

  • Only connect / disconnect board-under-test when power is off;

  • Ensure bypass capacitors are fully discharged before disconnecting board-under-test;

  • Make sure relays and switches are connected / disconnected only when power is completely off;

  • Avoid hot switching between tests:

    • Do not change voltage values or current ranges while the power supply is connected or on;

    • Do not turn off supplies between tests without allowing enough time for capacitors to discharge before starting the next test;

    • Do not use spring-loaded contacts that are at different heights, which could cause connection to any live supplies with undetermined sequences.

• Include voltage / current clamps to safeguard against datasheet violations.

• Manage test procedures:

  • Follow documented release process for test programs / procedures;

  • Audit test programs / procedures before release;

• • Maintain test programs / procedures under revision control.

Test Equipment:

• Prevent poorly connected, misaligned, and rotated test connections:

• Confirm mechanical safeguards exist to prevent accidental disconnect during test;

• Use connectors that only permit one-way orientation.

• Ensure that equipment has adequate grounding;

• Ensure that power sources are adequately conditioned / filtered;

• Follow regular schedule of diagnostics, maintenance, and calibration;

• Ensure that test equipment meets testing and safety requirements;

• Properly route and shield all sources of electrical energy;

• Shield board-under-test from mechanical hazards.

Assembly Flow:

• Prevent poorly connected, misaligned, and rotated components

• Use x-ray and/or optical inspection equipment;

• Place markers in silk screen to show proper device polarity / orientation;

• Use connectors that only permit one-way orientation.

System Design:

• Place electrical filters as close as possible to the device where the protection is needed;

• Select and place bypass capacitors to optimize the power supply performance and avoid unwanted resonance;

• Use well-regulated power supplies appropriate to the design;

• Use power supplies with overvoltage protection;

• Ensure voltage / current sources are capable of tolerating initial surge current;

• Ensure the design complies with all datasheet values, including power sequencing and ramp-rate requirements;

• If the system is designed for a hot-plugging application (e.g., USB), ensure the design tolerates side effects of hot plugging, such as inrush current and voltage sag;

• Minimize inductance in power supply connections in order to minimize radiated and conducted emissions;

• Design power circuits to prevent backwards current flow;

• Minimize overshoot and undershoot by using appropriate clamping devices;

• Avoid contention between output drivers;

• Avoid floating inputs, even for unused pins (e.g., by using pull-up / pull-down resistors);

• Select proper connectors between boards;

• Ensure proper heat dissipation;

• Distribute total board impedance as uniformly as possible;

• Ensure power routes are capable of sourcing adequate currents;

• Ensure impedance match between transmission line and load;

• Avoid ground loops;

• Use ground shields along signal paths to minimize crosstalk effects;

• Minimize impedance between separate ground planes;

• Review corner cases in software and eliminate undefined cases;

• Include error handling routines in software.

Dear Buniak，

     I am Sorry to trouble you again, and I have another question about ONET8501V application whick need your help；when the ONET8501V supply voltage is 0V( Power Off)，What is the Flt Pin output state? Low, high or uncertainty? Why? By the way, the Flt Pin is pulled up to 3v3 by 4.7k Resistor. Thank you for your great support.