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TI Home » TI E2E Community » Support Forums » Interface » High Speed Interface » High Speed Interface Forum » SN65LV1224B Data Clock Frequency Range for Locking
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SN65LV1224B Data Clock Frequency Range for Locking

This question is not answered
Scott Kerstein
Posted by Scott Kerstein
on Feb 27 2012 15:03 PM
Expert1205 points

If I have the ref clock running at 27MHz, what is the frequency range of the incoming data clock that this device will lock to?  The only spec the data sheet gives me is that the ref clock must be +/-100 ppm.

Thanks, in advance.

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  • Max Robertson
    Posted by Max Robertson
    on Feb 27 2012 15:39 PM
    Expert5975 points

    Hi Scott,

    The parallel clock rate corresponding to the serial data can be found by dividing the serial data rate by 12.  This rate should be within 200 ppm of the deserializer's reference clock rate.  In your case, the nominal serial data rate should be 324 Mbps.  If your reference clock is specified to within +/- 100 ppm, then the data rate should be specified to within +/- 100 ppm as well.  If your reference clock spec is tighter (e.g., +/- 50 ppm), then the serial data spec can be relaxed (e.g., to +/- 150 ppm) and vice-versa.

    Regards,
    Max Robertson
    Analog Applications Engineer
    Texas Instruments
    m-robertson@ti.com

     

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  • Mike Wolfe
    Posted by Mike Wolfe
    on Feb 28 2012 01:47 AM
    Intellectual785 points

    Hi Scott,

    If you are having difficulty meeting the timing requirements for this device you could consider using the DS92LV1224. The DS92LV1224 allows for +/-5% tolerance on the reference clock compared to the +/-100ppm of the SN65LV1224.

    Mike Wolfe

    DPS APPS / SVA

    DS92LV1224 B-LVDS
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