I´m Rainer from Hamilton Sundstrand Germany.
Some time ago, colleagues did a board for analog data acquisition with a DS90C241 24:1 LVDS serializer to output a continuous stream of measured values. In my current project I`m going to collect these data from up to 20 such sources and further process them within an FPGA. As there are not enough PLL sections available to recover all these asynchronuous data streams, the idea was to use SN65LVDS150 PLL building blocks to recover the LVDS clocks and feed them together with the LVDS datastreams into the FPGA. Does anybody has experience with this approach to tell me, whether it`s feasible? Or are there other solutions already prooven? The basic clock frequency of the DC90 chips on the data acquisition boards is 8MHz.
Thanks in advance for any input!
SN65LVDS150 is a PLL based frequency multiplier designed for developing TI Mux-It based serial inks that uses Mux-It serializers and de-serializers. The SN65LVDS150 is not a clock data recovery (CDR) device that can be used with other serdes devices that may have different coding schemes. Note the SN65LVDS150 has no serial data input. To de-serialize the data I suspect a DS90C124 de-serializer needs to be used.
An additional comment on the DS90C241 - as Atul noted, the DS90C124 would be the recommended Deserializer to use and then import the parallel LVCMOS data. The coding scheme used is unique to the chipset. Four bits are appended to the payload, two are rather simple and basically embed the clock information, the other two are rather complex and provide state machine sequence, data balancing and also data randomization. Decoding the serial data is not that trivial.
John GoldieDPS APPS / SVA
Atul, thanks for your comment, I will then have to use the 90C124....
John, thanks for your comments, I didn`t expect that decoding in nontrivial.... so I´ll use the 90C124.
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