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DP83849 JTAG Controller
I am using the DP83849 ethernet PHY in a JTAG chain with the TMS320C6745. What are the design considerations when using an emulator with the DSP? How will the DP83849 react if it shares the TRSTn with the DSP such that when the emulator is operational it deasserts TRSTn and runs with the DP83849 in BYPASS?
This will require some simulation and analysis to answer. This may take a few days due to the need for design support and availability next week. It will likely be the week of April 9th before I can resolve this.
My answers are below in a Q & A format.
Q1: At what level should TRSTn be held when the part is in operational mode and the JTAG is not being used?
A1: Holding TRSTn low during operational mode is the recommended approach. The DP83849 can be operated with TRSTn held high or low. The TMS320C6745 datasheet recommends holding TRSTn low during operational mode.
Q2: What level should TRSTn be held for the DP83849 when the part is in BYPASS?
A2: When the DP83849I is in BYPASS, TRSTn for the DP83849 should be high.
Q3: Are there any issues with using an emulator with the TMS320C6745 in the same chain as the DP83849I?
A3: Since the DP83849I can be bypassed, you can bring up the emulator on the TMS320C6745. In the emulator configuration you will need to enter the number of bypass bits for the IR register length on DP83849I (5 bits) and indicate that the JTAG chain includes that device besides the TMS320C6745 processor.
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