I am Peter from Hamilton Sundstrand in Germany.
We are going to use the LVDS SerDes 90C241 and 90C124 to transmit measurement data over backplane or cable.
Basically the 90C241 is supplied with 3.3V DC but riding high side on rated 115V AC. The receiver part 90C124 is
sitting on a different PCB in the system and is supplied only by 3.3V. The "DC" voltage difference between transmitter and receiver
could be 162V. We intend to use a supply clock value in the range of 5MHz to 10MHz.
Do you think to use a 100nF couple cap with high enough voltage (for example 250V) will lead to a stable LVDS communication without
any damage due to high voltage ??? (and will block the 115V rms AC)
In normal operation, all should be fine, but I would be concerned about the potential for large voltage transients getting into the part during powerup or power down. Under those conditions, it might be possible for a voltage spike far exceeding the power supply voltage to make it's way through the AC coupling cap and into the driver/receiver portion of the Serializer/Deserializer.
You might try controlling this with reverse biased diodes to the local Vcc and GND potentials at each end of the link. There are diodes like this on the inputs and outputs of our device, which are there to protect against ESD events, but the potential energy from a Power transient may well damage our internal devices - giving a path outside the chip for voltages outside the supply rails to get to GND would help protect the device.
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