it seems that the HOLD time of the SN65LV1023A must be under 4ns.
For an existing design we would violate this timing if we add all maximum timings in the design together.
Can we somehow reduce the hold time, for example if the temperature is between 25 and 60°C?
thanks,
Wolfgang
Wolfgang,
I wouldn't recommend operating the device outside of the spec limits. You would run the risk of issues showing up as device parameters shift over time/temperature/voltage and from lot to lot. It makes more sense to me to try to change the design to fit the spec rather than change the spec to fit the design.
One way to do this is to adjust the clock/data bus skew using delays. Another option if there is some margin on the set-up timing is to switch to the opposite clock polarity. The TCLK_R/F' pin can be used to select between rising-edge data strobing and falling-edge data strobing. Switching between these two modes is equivalent to advancing or delaying the clock line by 180 degrees (half a clock period).
Regards,Max RobertsonAnalog Applications EngineerTexas Instrumentsm-robertson@ti.com
Greetings -
I agree with Max, it is not recommended to operate outside the datasheet specifications. If the system has SET time margin, then another possible solution would be to add a logic buffer to the data lines to delay them with respect to the clock, this would trade off SET time for additional HOLD time to meet the 4ns spec.
Best Regards;
John GoldieDPS APPS / SVA / www.ti.com
Expanding upon the 4ns question, the nominal performance is expected to be less than 4ns, however the datasheet is set up for guaranteeing the limit over process, voltage, and temperature ranges. To ensure data capture over the PVT ranges. 4ns should be met. A limit is not published for a restricted temp range.
John Goldie
DPS APPS / SVA / www.ti.com
We use a level shifter at the moment in the data and clk path and a additional flipflop in the CLK. They have some variations in the propagation delay. If I count it all together I can not guarantee the hold time any more.
Thanks,
At 66MHz, the clock period is 15.15ns, the input stage specs 0.5ns set and 4 ns hold. This is less than 1/3 of the period for Data Valid. I would suggest to revisit the logic device between the host and the SER and perhaps if you have a wider Data Valid before the clock than needed, then add a delay to the 10 data lines with a buffer to push it back and gain more HOLD data valid to meet the requirements.
Best Wishes:
DPS APPS / SVA