Is DS10BR150 suitable for a 100MHz clock too?
Does DS10BR150 require a failsafe solution or not?
The DS10BR150 is a Buffer Repeater and supports DC to 1 Gbps (500MHz) operation. 100MHz Clock is fine.
I am checking on the failsafe feature and will advise. If your source, is removed, powered-off, tri-state, and the DS10BR150 is on, failsafe might be desirable. That can be done with an external pull up on the Plus, and a external pull down on the Minus, the 100 Ohm is internal. Set for a nominal common-mode point of the driver you are using also and at +100mV bias. This way the enabled 'BR150 device will sit at a stable known state, high in this case.
DPS APPS / SVA
thanks for the answer, but I haven't understood well how I can develop the failsafe. Which are the values of pull down and pull up resistors?
Here is a link to a detailed AP NOTE on Failsafe (AN-1194) http://www.ti.com/lit/an/snla051b/snla051b.pdf
If you have a 3.3V rail, try 1.5k pull up (plus to VCC) and 1.5k pull down (minus to GND), and assuming you only have the 100 Ohm across the pair (no source termination). This should give you about 1.1mA bias, and that across the 100 Ohm is 110mV Bias for a known HIGH outputs state.
I've already read the Application note but it explains all the procedure starting from the knowledge of (look at Fig.1)
1) VTC of device;
2) value of Vfsb.
Now I want to know how I can find the Vfsb, what it is and what is its aim, assuming that VTC is the same also for DS10BR150, since it isn't shown on the datasheet.
As described in the AN, one wants to set the bias to greater than the threshold, eg >+100mV. The RX input range is GND to VCC, a typical signal will be offset by a VOS, this could be 1.2V or 1.5V for simplicity. It depends on your driver you are using. The bias advised on above sets to 1/2 VCC, you can adjust resistors if you want or start there. The VTC is close to 0V, and inside the threshold range of -100mV to +100mV. In the example we set Vsfb to >100mV (approx 110mV).
Thank you very much, John!
Do you think that a 50 mV bias Voltage could be enough? So, if the bias is >100 mV we are sure that output logic value is high but this causes more distortion on the signal. Since VTC is about 0V and noise is not so high, I think is better set a 50 mV bias. What's your opinion?
Spec wise, biasing to 100mV is needed. (note 100mV comes from the LVDS standard not the part)
Since the thresholds are very tight, many do bias at >50mV without issue, this will distort less as you note, and is likely fine for the application.
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