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When I design my stackup, I always put two signal layers (X-Y) in a sandwich between two power layers. For sensitive signals, both power layers (if I can) are GND. If not, one of them is voltage, the other one is ground. Is your second group of addresses sandwiched between vcc and gnd, or only between two vcc layers (not recommended to do)?

The biggest problem of VCC layers is that they are usually cut in several sections because of the many voltages present on today boards. So the return path for the current could be very problematic. The second problem with the VCC layers is that their connection to GND is via capacitors, further complicating the road of the return path.

It is not to say that it won't work... but there are more chances for problems.

Thanks Albert,

Both the layers on which I have routed address bus are adjucent to eachother and both are sandwitched between Power and Ground layers. So, one of signal layers has reference as Ground and other has reference of Power plane. Further, for the address bus which has power plane as a reference, we are planing to give continuos copper plane over the routing.

We are proceeding for post layout SI analysis expecting if any problem will be there then it will be caught during SI analysis.

Regards,

Pavan

Thanks Albert,

Both the layers on which I have routed address bus are adjucent to eachother and both are sandwitched between Power and Ground layers. So, one of signal layers has reference as Ground and other has reference of Power plane. Further, for the address bus which has power plane as a reference, we are planing to give continuos copper plane over the routing. Let me know if this is acceptable?

Regards,

Pavan