Do the SN65LVDS1,
SN65LVDS2 LVDS devices have requirements on the MAXIMUM input rise (and fall)
Some application notes
state that long rise/fall times may lead a LVDS device to oscillate on the
“slow” input level changing.
What are the absolute maximum
input rise/fall times for the SN65LVDS1 IC to work without oscillation on the
input signal edges?
Unfortunately but their
datasheets contain no such information.
I am running simulations to confirm it. Give me a few days and i will get back to you.
I will be waiting.
16 days are left over.
Where is the answer and the modeling results?
Apologize for delay
The LVDS1 and LVDS2 are really old devices and getting the hspice models generated has taken a really long time than i expected. I dont have the modeling results. However what i was planning was to have a noise source on the input and sweep the rise and fall time and look at the output jitter.
I did talk to the design and the apps engineer who characterized this part. The feedback is that with slower rise and fall time, you will couple more noise into the part. The recommendation is not to go slower than 40% on rise and fall time of the bit period.
For example if you are running at 100MHz and the bit period is 10ns, you can go upto 4ns for rise and 4ns for fall time.
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