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DS90UB953-Q1: MIPI-CSI clock and throughput

Part Number: DS90UB953-Q1

Hi,

We are using the 953/954 SerDes with a CMOS sensor. About the 953 MIPI-CSI input, the datasheet says "Up to 4 Data Lanes at 832 Mbps Per Each Lane". This indicates a total throughput of around 3.2Gbps for 4 MIPI lanes.

I want to confirm if the above statement means the MIPI CLK can not be beyond 416MHz, or it is talking about the throughput regardless how fast my MIPI CLK is.

Considering the following scenario:

The sensor is able to provide 4K@60FPS RAW10 and has 4 MIPI lanes with a default 1.44Gbps/lane (720MHz). However we only need run FHD@60FPS RAW10. Considering the load throughput, it has around 1.2Gbps in total and 300Mbps/lane.

So using the default 1.44Gbps/lane mode, the MIPI signals will stay in Low Power after bursting out the effective data in High Speed. In this case, we have a 720MHz MIPI CLK which is higher than the 416MHz. But the effective throughput is only 300Mbps which is lower than the 832Mbps.

Does this setting work with the 953 Serializer? If not, is there anyway to overclock the 953 because our sensor vendor does not recommend us to lower the sensor clock.

Thanks in advance,

Harry

  • Hello Harry,

    Yes, for the DS90UB953-Q1 both the max continuous and peak CSI rate should remain at or below 832Mbps/lane.
    Ideally the CSI clock rate of the sensor could be adjusted independantly from the sensor reference clock.
    The 953 does have capability to output a programmable reference clock to the sensor.

    TI does have Serializer devices supporting higher CSI-2 input rates, but this information is available only under NDA.

    Liam Keese

    FPD-Link Systems & Applications


    Training on FPD-Link Serializer Deserializer devices and system: https://training.ti.com/fpd-link-learning-center

    More information on IVI or ADAS FPD-Link products: http://www.ti.com/interface/fpd-link-serdes/overview.html

  • In reply to Liam Keese:

    Hi Liam,

    Thanks for your explanation. The sensor vendor did send us register settings to adjust the MIPI CLK. However they do not recommend us to do that, telling us the performance is not guarantied.

    We are also aware of 953's ability to output different ref clock to sensor.

    Quote from your reply: "Ideally the CSI clock rate of the sensor could be adjusted independantly from the sensor reference clock.
    The 953 does have capability to output a programmable reference clock to the sensor. "

    I am a little bit confused here. Were you trying to say "independently" or "dependently" ? Please confirm, thanks.

    After lowering the MIPI rate to within 800Mbps, we can successfully run our whole system from the camera to 953 to 954 to ISP, and see the video in the monitor.


    We do have NDA with TI. Can you inform me the best way to move forward talking about the higher rate Serializer?

    Thanks,

    Harry
  • In reply to Liam Keese:

    Hi Liam,

    Could you please update regarding my new questions?

    Harry
  • In reply to Hmmm:

    Hello,
    Sorry for the confusion. I simply meant to state that the input CSI-2 clock provided to the DS90UB953 is somewhat independant of the FPD-Link line rate as long as it does not exceed the max CSI-2 rate supported.
    The flexible M/N dividers on the 953 CLK_OUT can provide many options to drive an image sensor at a variety of CSI-2 clock output rates.

    Liam Keese

    FPD-Link Systems & Applications


    Training on FPD-Link Serializer Deserializer devices and system: https://training.ti.com/fpd-link-learning-center

    More information on IVI or ADAS FPD-Link products: http://www.ti.com/interface/fpd-link-serdes/overview.html

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