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SN65LVDT101: LVDS to 3.3V PECL

Part Number: SN65LVDT101

Dears,

Our customer have some questions about SN65LVDT101. In his application,  SN65LVDT101 is connected to MC100EP195 (On Semiconductor), which is a 3.3V ECL programmable delay chip. The schematic is as follows:

The 1.3V is supplied by a LDO, the max current the LDO could supply is 200mA. While, the customer measured the voltage of 1.3V point, it's value is 2.7V not 1.3V, the output voltage swing of  SN65LVDT101 is also incorrect.  Then he removed two 50 Ohms termination resistors and detected again,  the output of LDO is 1.3, it's correct. He used a Source Voltage to replace LDO, the output voltage swing is also incorrect. 

Then he tried another method the Thevenin Termination. This time the output voltage swing is correct.

I know Thevenin Termination is based on standard LVPECL termination, but why standard LVPECL termination couldn't work normal in this application? 

Any comments or suggestions are welcome.

Regards,

Ricardo

  • Hello,

    I am not sure what you mean when you said the customer measured the voltage of 1.3V point, it's value is 2.7V?? It needs to be 1.3V for this to work. The 2 circuits should be equivalent and should both work. There may be an issue with how the 1.3V supply is connected and its ground reference.

    Regards,
    Yaser
  • In reply to Yaser Ibrahim:

    Hi Yaser,

    Thanks for your help.

    I'm not very clear about mechanism of LVPECL, There have some questions I want to confirm.

    (1). It is introduced in our Application Report SLLA120 that the output stage of LVPECL. It shows that "the emitters of the pair of followers are around VCC – 1.3 V", Does this mean the voltage of point A is VCC – 1.3 V? And why the drop voltage of 50 Ohms resistor is 0.7V?

    (2). How the output swing voltage of LVPECL is built?

    (3). The common voltage of LVPECL is 2V. What is the direction of the current when it flows through the 50 Ohms resistor?

    Regards,

    Ricardo

  • In reply to Ricardo Li:

    Hi Ricardo,
    I believe the issue you are having with the LDO is that it is designed only to source current. In this application it would need to sink current. This is why the thevenin termination can maintain the correct output common mode voltage.

    For question #3 the current will flow from positive to negative. From the output to the Vcc-2V termination.

    Regards,
    Lee
  • In reply to Lee Sledjeski:

    Hi Lee,

    I understand now, Thanks for your help.

    Regards,

    Ricardo 

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