Part Number: DS90UH925QSEVB
I would like to get your point of view on the test method and tool for measuring the insertion loss and other S-parameters on such this FPDLink Eval board or other FPDLink boards.
For an accurate measurement, the VNA is the best solution, but for using it, we would need to add SMA at the closest level of the chip. Unfortunately adding such extra connector would cause impedance discontinuity and therefore negatively impacts signal integrity.
Do you agree with me?
What would be your recommendation to test those parameters? To use a time domain methods ? Do you have any test method or standard to provide?
Thank you for your support,
Time domain will have the same impedance discontinuity challenge.
I do the VNA SOLT calibration with the adaptors I need in place, so that the adapter effect is removed.
This requires a SOLT with SMA connectors & mating genders in your case. With this method you extend the calibration plane to the end of the SMA adapters and get an accurate measurement.
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In reply to Mike Leister:
Thank you for your answer.I will reformulate a bit: if I kept the SMA connector, for sure, I will get the same impedance discontinuity challenge for any test method.
My idea was not add any SMA connector on the board for the measurement and, instead, to use another method to derive the Diff Insertion Loss from TDR measurement (SET2DIL) by using a 2-port measurement (so using the 2 Diff port of the Board connector) instead of the 4-port measurement (using the 2 Diff port of the Board connector and the 2 SMA connector port at the chip level).
In reply to Guillaume Girod:
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