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Linux/DS90UB964-Q1: UB964-Q1 and UB913 BCC communicate error

Part Number: DS90UB964-Q1

Tool/software: Linux

I am debug-ing DS90UB964 and DS90UB913 control channel.

the current condition:

1)Less than 20% probability to correctly write 913 registers

2)964‘s status reg have error.

       0x4D's val is:0x33/0x51(two board have diff val)

       0x4E's val is:0xe5

3)try digital reset,but i could not see 0x01 reg's reset bit self clean

       write_reg(0x01, 0x01)-----could not see the val become 0 again

Please help to see this issue,thank you very much.

  • Hello,
    Which side is the I2C master? Are the local transactions working correctly on the deserializer/host side if the serializer is on the remote side?
    For local access issue make sure its not strapped to the wrong address and the pullup resistors are the correct values.


    Training on FPD-Link Serializer Deserializer devices and system: https://training.ti.com/fpd-link-learning-center

    More information on IVI or ADAS FPD-Link products: http://www.ti.com/interface/fpd-link-serdes/overview.html

  • In reply to Palaniappan Manickam:

    Thanks for reply.

    UB964 is the I2C master, and UB913 is on the remote side. Host(a arm soc) can communicate to UB964.

    I found when enable "I2C Pass-Through All Transactions ", and set the I2C address to the true UB913 address(not the alias id).CPU can successfully communicate with UB913.

    But,0x4D/0x4E reg stil show errors:

    0x4D's val is 0x33

    0x4E's val is 0xe5

  • In reply to user5344592:

    the RX_Status register showed your link have many errors, which could make the I2C link fail.
    please check your link design between UB913a and UB964 firstly to secure it has NO bit error including back-channel CRC error:
    what is the cable and connector? what is the S parameter?
    POC voltage?
    PCLK?
    Camera design layout?
    POC network design?
    ....
    after you resolve the CRC error issue, I think the i2c reg. read/write also can be correct.

    regards,
    Steven
  • In reply to Junqiang Shi:

    Schematic:

    PCB:

  • In reply to user5344592:

    the poc circuit design has some problem. pls follow up ub964EVM board design, you can not use only 10uH inductor. for detailed poc operation, pls visit www.ti.com/fpd-link on on-line video training.


    regards
    Steven
  • In reply to Junqiang Shi:

    This design is also from TI Design Guide.(TIDA-01323_Camera_SCH.pdf)

    In addition, I found that setting AEQ_1ST_LOCK_MODE to 1 improved the loss of LOCK,

    So I want to know that can we correct the lose LOCK problem by setting some registers?

  • In reply to user5344592:

    I get to know your PoC circuit design is from TI's UB953 refer. design, but this is NOT available for UB913a, please follow up TI's UB913a EVM board refer. design in TI.com.
    the reason is that UB913a and UB953 has different signal bandwidth in the cable, for details, you can refer to www.ti.com/FPD-Link on-line video training, thanks.

    regards,
    Steven
  • In reply to user5344592:

    equalizer setting can help the link jitter margin, but it is NOT needed for the link application since TI's equalizer is adaptive. you should improve the link noise margin to resolve this issue, PoC is one of reasons. you also can check the cable, layout (the picture you pasted sounds issue, the R- pin signal?), impedance control, power supply noise etc.

    best regards,
    Steven
  • In reply to Junqiang Shi:

    Found yesterday,
    After setting FPD3_MODE to RAW10, the lost lock problem is gone(Our camera is RAW10 mode). Does this setting will affect LOCK or BCC_CRC?

  • In reply to user5344592:

    not, if the link is reliable. the work mode would impact the line rate. if the line rate is decreased, the system margin would be improved, which is helpful for the unlocked issue.

    Steven

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